ARM: DRA7: Add macros for voltage values for all OPPs
Define specific macros for the voltage values for all voltage domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH. No separate macros are defined for VD_MPU and VD_CORE at OPP_OD and OPP_HIGH as these use the same values as OPP_NOM. The current macros will be used as common macros that can be redefined appropriately based on a selected OPP configuration at build time. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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@ -240,11 +240,21 @@
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#define VDD_MM_ES2_LOW 880
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/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
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#define VDD_MPU_DRA7 1150
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#define VDD_CORE_DRA7 1150
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#define VDD_EVE_DRA7 1060
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#define VDD_GPU_DRA7 1060
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#define VDD_IVA_DRA7 1060
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#define VDD_MPU_DRA7_NOM 1150
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#define VDD_CORE_DRA7_NOM 1150
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#define VDD_EVE_DRA7_NOM 1060
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#define VDD_GPU_DRA7_NOM 1060
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#define VDD_IVA_DRA7_NOM 1060
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/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
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#define VDD_EVE_DRA7_OD 1150
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#define VDD_GPU_DRA7_OD 1150
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#define VDD_IVA_DRA7_OD 1150
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/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
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#define VDD_EVE_DRA7_HIGH 1250
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#define VDD_GPU_DRA7_HIGH 1250
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#define VDD_IVA_DRA7_HIGH 1250
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/* Efuse register offsets for DRA7xx platform */
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#define DRA752_EFUSE_BASE 0x4A002000
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@ -276,7 +286,14 @@
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/* STD_FUSE_OPP_VMIN_MPU_4 */
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#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
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/* Common Efuse register macros */
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/* Common voltage and Efuse register macros */
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/* DRA74x/DRA75x/DRA72x */
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#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM
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#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM
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#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM
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#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM
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#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM
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#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM
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#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
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#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM
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