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ARM: cp15: setup mmu and enable dcache

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This has been tested on at91sam9263 and STN8815.
Again, I didn't check if it has bad effects
on non-arm926 cores.

Initially I had a "done" bit to only set up page tables
at the beginning. However, since the aligmnent requirement
was for the whole object file, this extra integer tool 16kB
in BSS, so I chose to remove it.

Also, note not all boards use PHYS_SDRAM, but it looks like
it's the most used name (more than CONFIG_SYS_DRAM_BASE for
example).

Portions of this work were supported by funding from
the CE Linux Forum.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher 2010-09-17 13:10:29 +02:00 committed by Wolfgang Denk
parent 55e97429d1
commit 880eff5cfb
1 changed files with 51 additions and 0 deletions
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51
arch/arm/lib/cache-cp15.c
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@ -25,6 +25,15 @@
#include <asm/system.h>
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
#define CACHE_SETUP 0x1a
#else
#define CACHE_SETUP 0x1e
#endif
DECLARE_GLOBAL_DATA_PTR;
static void cp_delay (void)
{
volatile int i;
@ -32,6 +41,40 @@ static void cp_delay (void)
/* copro seems to need some delay between reading and writing */
for (i = 0; i < 100; i++)
nop();
asm volatile("" : : : "memory");
}
/* to activate the MMU we need to set up virtual memory: use 1M areas in bss */
static inline void mmu_setup(void)
{
static u32 __attribute__((aligned(16384))) page_table[4096];
bd_t *bd = gd->bd;
int i, j;
u32 reg;
/* Set up an identity-mapping for all 4GB, rw for everyone */
for (i = 0; i < 4096; i++)
page_table[i] = i << 20 | (3 << 10) | 0x12;
/* Then, enable cacheable and bufferable for RAM only */
for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
for (i = bd->bi_dram[j].start >> 20;
i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20;
i++) {
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
}
}
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
: : "r" (page_table) : "memory");
/* Set the access control to all-supervisor */
asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0));
/* and enable the mmu */
reg = get_cr(); /* get control reg. */
cp_delay();
set_cr(reg | CR_M);
}
/* cache_bit must be either CR_I or CR_C */
@ -39,6 +82,9 @@ static void cache_enable(uint32_t cache_bit)
{
uint32_t reg;
/* The data cache is not active unless the mmu is enabled too */
if (cache_bit == CR_C)
mmu_setup();
reg = get_cr(); /* get control reg. */
cp_delay();
set_cr(reg | cache_bit);
@ -49,6 +95,11 @@ static void cache_disable(uint32_t cache_bit)
{
uint32_t reg;
if (cache_bit == CR_C) {
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
flush_cache(0, ~0);
}
reg = get_cr();
cp_delay();
set_cr(reg & ~cache_bit);