ARM: add SBx81LIFKW board
This is a series of line cards for Allied Telesis's SBx8100 chassis switch. The CPU block is common to the SBx81GS24a, SBx81XS6, SBx81XS16 and SBx81GT40 cards collectively referred to as SBx81LIFKW in u-boot. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham
Stefan Roese
parent
2c3c6bc6fb
commit
87a62bce28
133
arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
Normal file
133
arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
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@ -0,0 +1,133 @@
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "kirkwood.dtsi"
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#include "kirkwood-6281.dtsi"
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/ {
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model = "Allied Telesis SBx81LIFKW Board";
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compatible = "atl,SBx81LIFKW", "marvell,kirkwood-88f6281",
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"marvell,kirkwood";
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memory {
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device_type = "memory";
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reg = <0x00000000 0x08000000>; /* 128 MB */
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};
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chosen {
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bootargs = "console=ttyS0,115200n8 earlyprintk";
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stdout-path = &uart0;
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};
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aliases {
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ethernet0 = ð0;
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i2c0 = &i2c0;
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spi0 = &spi0;
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};
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dsa {
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compatible = "marvell,dsa";
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#address-cells = <2>;
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#size-cells = <0>;
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dsa,ethernet = <ð0>;
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dsa,mii-bus = <&mdio>;
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status = "okay";
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switch@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1 0>;
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port@0 {
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reg = <0>;
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label = "internal0";
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};
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port@1 {
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reg = <1>;
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label = "internal1";
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};
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port@8 {
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reg = <8>;
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label = "internal8";
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@9 {
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reg = <9>;
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label = "internal9";
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@10 {
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reg = <10>;
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label = "cpu";
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};
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
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reg = <0>;
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spi-max-frequency = <50000000>;
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mode = <0>;
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partition@u-boot {
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reg = <0x00000000 0x00c00000>;
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label = "u-boot";
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};
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partition@u-boot-env {
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reg = <0x00c00000 0x00040000>;
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label = "u-boot-env";
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};
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partition@unused {
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reg = <0x00100000 0x00f00000>;
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label = "unused";
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};
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};
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};
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&i2c0 {
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status = "okay";
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eeprom@52 {
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compatible = "atmel,24c04";
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reg = <0x52>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&mdio {
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status = "okay";
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};
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ð0 {
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status = "okay";
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ethernet0-port@0 {
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speed = <1000>;
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duplex = <1>;
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};
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};
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&pciec {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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};
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@ -59,6 +59,9 @@ config TARGET_NAS220
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config TARGET_NSA310S
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bool "Zyxel NSA310S"
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config TARGET_SBx81LIFKW
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bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
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endchoice
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config SYS_SOC
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@ -81,5 +84,6 @@ source "board/Seagate/dockstar/Kconfig"
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source "board/Seagate/goflexhome/Kconfig"
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source "board/Seagate/nas220/Kconfig"
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source "board/zyxel/nsa310s/Kconfig"
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source "board/alliedtelesis/SBx81LIFKW/Kconfig"
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endif
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12
board/alliedtelesis/SBx81LIFKW/Kconfig
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12
board/alliedtelesis/SBx81LIFKW/Kconfig
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@ -0,0 +1,12 @@
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if TARGET_SBx81LIFKW
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config SYS_BOARD
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default "SBx81LIFKW"
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config SYS_VENDOR
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default "alliedtelesis"
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config SYS_CONFIG_NAME
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default "SBx81LIFKW"
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endif
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7
board/alliedtelesis/SBx81LIFKW/MAINTAINERS
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7
board/alliedtelesis/SBx81LIFKW/MAINTAINERS
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@ -0,0 +1,7 @@
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SBx81LIFKW BOARD
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M: Chris Packham <chris.packham@alliedtelesis.co.nz>
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S: Maintained
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F: board/alliedtelesis/SBx81LIFKW/
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F: include/configs/SBx81LIFKW
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F: configs/SBx81LIFKW_defconfig
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F: arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
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7
board/alliedtelesis/SBx81LIFKW/Makefile
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7
board/alliedtelesis/SBx81LIFKW/Makefile
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2010, 2018
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# Allied Telesis <www.alliedtelesis.com>
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#
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obj-y += sbx81lifkw.o
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47
board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
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47
board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
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@ -0,0 +1,47 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2018 Allied Telesis
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#
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# Refer docs/README.kwimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM spi # Boot from SPI flash
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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DATA 0xffd100e0 0x1b1b1b1b
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DATA 0xffd20134 0xffffffff
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DATA 0xffd20138 0x009fffff
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DATA 0xffd20154 0x00000000
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DATA 0xffd2014c 0x00000000
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DATA 0xffd20148 0x00000001
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# Dram initalization for 1 x x16
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# DDR II Micron part number MT47H64M16HR-3
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# MClk 333MHz, Size 128MB, ECC disable
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#
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DATA 0xffd01400 0x43000618
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DATA 0xffd01404 0x35143000
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DATA 0xffd01408 0x11012227
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DATA 0xffd0140c 0x00000819
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DATA 0xffd01410 0x0000000d
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DATA 0xffd01414 0x00000000
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DATA 0xffd01418 0x00000000
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DATA 0xffd0141c 0x00000632
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DATA 0xffd01420 0x00000040
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DATA 0xffd01424 0x0000f07f
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DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
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DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
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DATA 0xffd01508 0x10000000
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DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
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DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
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DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
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DATA 0xffd01494 0x00030000
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DATA 0xffd01498 0x00000000
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DATA 0xffd0149c 0x0000e803
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DATA 0xffd01480 0x00000001
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# End of Header extension
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DATA 0x0 0x0
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187
board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
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187
board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
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@ -0,0 +1,187 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010, 2018
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* Allied Telesis <www.alliedtelesis.com>
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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/* Note: GPIO differences between specific boards
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*
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* We're trying to avoid having multiple build targets for all the Kirkwood
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* based boards one area where things tend to differ is GPIO usage. For the
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* most part the GPIOs driven by the bootloader are similar enough in function
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* that there is no harm in driving them.
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*
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* XZ4 XS6 XS16 GS24A GT40 GP24A GT24A
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* GPIO39 - INT(<) NC MUX_RST_N(>) NC POE_DIS_N(>) NC
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*/
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#define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
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BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
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BIT(10))
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#define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7))
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#define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27))
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#define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1))
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#define MV88E6097_RESET 27
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DECLARE_GLOBAL_DATA_PTR;
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struct led {
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u32 reg;
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u32 value;
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u32 mask;
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};
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struct led amber_solid = {
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MVEBU_GPIO0_BASE,
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BIT(10),
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BIT(18) | BIT(10)
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};
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struct led green_solid = {
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MVEBU_GPIO0_BASE,
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BIT(18) | BIT(10),
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BIT(18) | BIT(10)
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};
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struct led amber_flash = {
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MVEBU_GPIO0_BASE,
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0,
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BIT(18) | BIT(10)
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};
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struct led green_flash = {
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MVEBU_GPIO0_BASE,
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BIT(18),
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BIT(18) | BIT(10)
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};
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static void status_led_set(struct led *led)
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{
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clrsetbits_le32(led->reg, led->mask, led->value);
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}
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(SBX81LIFKW_OE_VAL_LOW,
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SBX81LIFKW_OE_VAL_HIGH,
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SBX81LIFKW_OE_LOW, SBX81LIFKW_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_SPI_SCn,
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP4_UART0_RXD,
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MPP5_UART0_TXD,
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MPP6_SYSRST_OUTn,
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MPP7_PEX_RST_OUTn,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_GPO,
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MPP11_GPIO,
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MPP12_GPO,
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MPP13_GPIO,
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MPP14_GPIO,
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MPP15_UART0_RTS,
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MPP16_UART0_CTS,
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MPP17_GPIO,
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MPP18_GPO,
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MPP19_GPO,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_GPIO,
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MPP41_GPIO,
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MPP42_GPIO,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO,
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MPP48_GPIO,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* Power-down unused subsystems. The required
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* subsystems are:
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*
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* GE0 b0
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* PEX0 PHY b1
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* PEX0.0 b2
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* TSU b5
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* SDRAM b6
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* RUNIT b7
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*/
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writel((BIT(0) | BIT(1) | BIT(2) |
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BIT(5) | BIT(6) | BIT(7)),
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KW_CPU_REG_BASE + 0x1c);
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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status_led_set(&amber_solid);
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return 0;
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}
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#ifdef CONFIG_MV88E61XX_SWITCH
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/* Configure and enable Switch and PHY */
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void reset_phy(void)
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{
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/* Ensure the 88e6097 gets at least 10ms Reset
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*/
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kw_gpio_set_value(MV88E6097_RESET, 0);
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mdelay(20);
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kw_gpio_set_value(MV88E6097_RESET, 1);
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mdelay(20);
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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status_led_set(&green_flash);
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return 0;
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}
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#endif
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33
configs/SBx81LIFKW_defconfig
Normal file
33
configs/SBx81LIFKW_defconfig
Normal file
@ -0,0 +1,33 @@
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CONFIG_ARM=y
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CONFIG_KIRKWOOD=y
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CONFIG_SYS_TEXT_BASE=0x00600000
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CONFIG_TARGET_SBx81LIFKW=y
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CONFIG_IDENT_STRING="\nSBx81LIFKW"
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CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw"
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# CONFIG_SYS_MALLOC_F is not set
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CONFIG_BOOTDELAY=3
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CONFIG_SILENT_CONSOLE=y
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CONFIG_SILENT_U_BOOT_ONLY=y
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CONFIG_HUSH_PARSER=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_I2C=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_DHCP=y
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CONFIG_BOOTP_NTPSERVER=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_SNTP=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_DM=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_MVTWSI=y
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CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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# CONFIG_MMC is not set
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_SPI=y
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CONFIG_KIRKWOOD_SPI=y
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124
include/configs/SBx81LIFKW.h
Normal file
124
include/configs/SBx81LIFKW.h
Normal file
@ -0,0 +1,124 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 Allied Telesis <www.alliedtelesis.co.nz>
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*/
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#ifndef _CONFIG_SBX81LIFKW_H
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#define _CONFIG_SBX81LIFKW_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
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#define CONFIG_KW88F6281 1 /* SOC Name */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
|
||||
#define CONFIG_BUILD_TARGET "u-boot.kwb"
|
||||
|
||||
/* additions for new ARM relocation support */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
|
||||
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
|
||||
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
|
||||
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
|
||||
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
|
||||
#define CONFIG_KIRKWOOD_GPIO 1
|
||||
|
||||
#define CONFIG_MISC_INIT_R /* call misc_init_r */
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
|
||||
#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
|
||||
|
||||
/*
|
||||
* Serial Port configuration
|
||||
* The following definitions let you select what serial you want to use
|
||||
* for your console driver.
|
||||
*/
|
||||
|
||||
#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
|
||||
|
||||
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
|
||||
#define MTDPARTS_MTDOOPS "errlog"
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
|
||||
#define CONFIG_ENV_SIZE 0x02000
|
||||
#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */
|
||||
|
||||
/*
|
||||
* U-Boot bootcode configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
|
||||
|
||||
/* size in bytes reserved for initial data */
|
||||
|
||||
#include <asm/arch/config.h>
|
||||
/* There is no PHY directly connected so don't ask it for link status */
|
||||
#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
|
||||
|
||||
/*
|
||||
* Other required minimal configurations
|
||||
*/
|
||||
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
|
||||
#define CONFIG_NR_DRAM_BANKS 4
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
#define CONFIG_NET_MULTI /* specify more that one ports available */
|
||||
#define CONFIG_MII /* expose smi over miiphy interface */
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
|
||||
#define CONFIG_PHY_BASE_ADR 0x01
|
||||
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
|
||||
#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch */
|
||||
#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
|
||||
#define CONFIG_MV88E61XX_PHY_PORTS 0x303 /* Pt0,1,8,9 */
|
||||
#define CONFIG_MV88E61XX_CPU_PORT 10 /* 10(CPU) */
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* Time settings
|
||||
*/
|
||||
#define CONFIG_RTC_MV
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
|
||||
|
||||
#endif /* _CONFIG_SBX81LIFKW_H */
|
||||
Loading…
Reference in New Issue
Block a user