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Merge branch 'master' of http://git.denx.de/u-boot-samsung

Browse Source
This commit is contained in:
Tom Rini 2014-11-25 11:10:01 -05:00
commit 878cd63e02
36 changed files with 787 additions and 87 deletions
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7
arch/arm/cpu/armv7/exynos/Kconfig
View File

@ -46,11 +46,16 @@ config TARGET_SMDK5420
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_PEACH_PIT
config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_PEACH_PIT
bool "Peach Pit board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
endchoice
config SYS_SOC

19
arch/arm/cpu/armv7/exynos/clock.c
View File

@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
else if (proid_is_exynos5250() || proid_is_exynos5420())
else if (proid_is_exynos5250() || proid_is_exynos5420()
|| proid_is_exynos5800())
div = PLL_DIV_65536;
else
return 0;
@ -1581,7 +1582,7 @@ static unsigned long exynos4_get_i2c_clk(void)
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
@ -1617,7 +1618,7 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
@ -1630,7 +1631,7 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
} else {
@ -1643,7 +1644,7 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
} else {
@ -1654,7 +1655,7 @@ unsigned long get_mmc_clk(int dev_index)
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);
else
exynos5_set_mmc_clk(dev_index, div);
@ -1668,7 +1669,7 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_lcd_clk();
else
return exynos5_get_lcd_clk();
@ -1682,7 +1683,7 @@ void set_lcd_clk(void)
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
else if (proid_is_exynos5420())
else if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_lcd_clk();
}
}
@ -1696,7 +1697,7 @@ void set_mipi_clk(void)
int set_spi_clk(int periph_id, unsigned int rate)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
} else {

2
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
View File

@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
void system_clock_init(void)
{
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_system_clock_init();
else
exynos5250_system_clock_init();

29
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
View File

@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
+ DMC_OFFSET);
pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
if (CONFIG_NR_DRAM_BANKS > 4) {
/* Need both controllers. */
mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
mem->chips_per_channel = 2;
mem->chips_to_configure = 2;
} else {
/* 2GB requires a single controller */
mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
}
/* Enable PAUSE for DREX */
setbits_le32(&clk->pause, ENABLE_BIT);
@ -832,6 +842,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
/*
* As per Exynos5800 UM ver 0.00 section 17.13.2.1
* CONCONTROL register bit 3 [update_mode], Exynos5800 does not
* support the PHY initiated update. And it is recommended to set
* this field to 1'b1 during initialization
*
* When we apply PHY-initiated mode, DLL lock value is determined
* once at DMC init time and not updated later when we change the MIF
* voltage based on ASV group in kernel. Applying MC-initiated mode
* makes sure that DLL tracing is ON so that silicon is able to
* compensate the voltage variation.
*/
val = readl(&drex0->concontrol);
val |= CONCONTROL_UPDATE_MODE;
writel(val , &drex0->concontrol);
val = readl(&drex1->concontrol);
val |= CONCONTROL_UPDATE_MODE;
writel(val , &drex1->concontrol);
return 0;
}
#endif

2
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@ -837,7 +837,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_pinmux_config(peripheral, flags);
else if (proid_is_exynos5250())
return exynos5_pinmux_config(peripheral, flags);

27
arch/arm/cpu/armv7/exynos/power.c
View File

@ -53,10 +53,37 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
}
}
void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
{
struct exynos4412_power *power =
(struct exynos4412_power *)samsung_get_base_power();
if (enable) {
/* Enabling USBHOST_PHY */
setbits_le32(&power->usbhost_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
setbits_le32(&power->hsic1_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
setbits_le32(&power->hsic2_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
} else {
/* Disabling USBHOST_PHY */
clrbits_le32(&power->usbhost_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&power->hsic1_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&power->hsic2_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
}
}
void set_usbhost_phy_ctrl(unsigned int enable)
{
if (cpu_is_exynos5())
exynos5_set_usbhost_phy_ctrl(enable);
else if (cpu_is_exynos4())
if (proid_is_exynos4412())
exynos4412_set_usbhost_phy_ctrl(enable);
}
static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)

10
arch/arm/cpu/armv7/exynos/spl_boot.c
View File

@ -195,10 +195,16 @@ void copy_uboot_to_ram(void)
void (*end_bootop_from_emmc)(void);
#endif
#ifdef CONFIG_USB_BOOTING
u32 (*usb_copy)(void);
int is_cr_z_set;
unsigned int sec_boot_check;
/*
* Note that older hardware (before Exynos5800) does not expect any
* arguments, but it does not hurt to pass them, so a common function
* prototype is used.
*/
u32 (*usb_copy)(u32 num_of_block, u32 *dst);
/* Read iRAM location to check for secondary USB boot mode */
sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
@ -240,7 +246,7 @@ void copy_uboot_to_ram(void)
*/
is_cr_z_set = config_branch_prediction(0);
usb_copy = get_irom_func(USB_INDEX);
usb_copy();
usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
config_branch_prediction(is_cr_z_set);
break;
#endif

3
arch/arm/dts/Makefile
View File

@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb
exynos5420-peach-pit.dtb \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \

11
arch/arm/dts/exynos4412-odroid.dts
View File

@ -67,4 +67,15 @@
div = <0x3>;
index = <4>;
};
ehci@12580000 {
compatible = "samsung,exynos-ehci";
reg = <0x12580000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
phy {
compatible = "samsung,exynos-usb-phy";
reg = <0x125B0000 0x100>;
};
};
};

4
arch/arm/dts/exynos5250-snow.dts
View File

@ -131,11 +131,11 @@
};
ehci@12110000 {
samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */
samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */
samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
};
tmu@10060000 {

157
arch/arm/dts/exynos5800-peach-pi.dts Normal file
View File

@ -0,0 +1,157 @@
/*
* SAMSUNG/GOOGLE Peach-Pit board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "exynos54xx.dtsi"
/ {
model = "Samsung/Google Peach Pi board based on Exynos5800";
compatible = "google,pit-rev#", "google,pit",
"google,peach", "samsung,exynos5800", "samsung,exynos5";
config {
google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
aliases {
serial0 = "/serial@12C30000";
console = "/serial@12C30000";
pmic = "/i2c@12ca0000";
};
dmc {
mem-manuf = "samsung";
mem-type = "ddr3";
clock-frequency = <800000000>;
arm-frequency = <1700000000>;
};
tmu@10060000 {
samsung,min-temp = <25>;
samsung,max-temp = <125>;
samsung,start-warning = <95>;
samsung,start-tripping = <105>;
samsung,hw-tripping = <110>;
samsung,efuse-min-value = <40>;
samsung,efuse-value = <55>;
samsung,efuse-max-value = <100>;
samsung,slope = <274761730>;
samsung,dc-value = <25>;
};
/* MAX77802 is on i2c bus 4 */
i2c@12ca0000 {
clock-frequency = <400000>;
power-regulator@9 {
compatible = "maxim,max77802-pmic";
reg = <0x9>;
};
};
i2c@12cd0000 { /* i2c7 */
clock-frequency = <100000>;
soundcodec@20 {
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
edp-lvds-bridge@48 {
compatible = "parade,ps8625";
reg = <0x48>;
};
};
sound@3830000 {
samsung,codec-type = "max98090";
};
i2c@12e10000 { /* i2c9 */
clock-frequency = <400000>;
tpm@20 {
compatible = "infineon,slb9645-tpm";
reg = <0x20>;
};
};
spi@12d30000 { /* spi1 */
spi-max-frequency = <50000000>;
firmware_storage_spi: flash@0 {
reg = <0>;
/*
* A region for the kernel to store a panic event
* which the firmware will add to the log.
*/
elog-panic-event-offset = <0x01e00000 0x100000>;
elog-shrink-size = <0x400>;
elog-full-threshold = <0xc00>;
};
};
spi@12d40000 { /* spi2 */
spi-max-frequency = <4000000>;
spi-deactivate-delay = <200>;
cros-ec@0 {
reg = <0>;
compatible = "google,cros-ec";
spi-half-duplex;
spi-max-timeout-ms = <1100>;
spi-frame-header = <0xec>;
ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
/*
* This describes the flash memory within the EC. Note
* that the STM32L flash erases to 0, not 0xff.
*/
#address-cells = <1>;
#size-cells = <1>;
flash@8000000 {
reg = <0x08000000 0x20000>;
erase-value = <0>;
};
};
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
};
xhci@12400000 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
};
fimd@14400000 {
samsung,vl-freq = <60>;
samsung,vl-col = <1920>;
samsung,vl-row = <1080>;
samsung,vl-width = <1920>;
samsung,vl-height = <1080>;
samsung,vl-clkp;
samsung,vl-dp;
samsung,vl-bpix = <4>;
samsung,vl-hspw = <80>;
samsung,vl-hbpd = <172>;
samsung,vl-hfpd = <60>;
samsung,vl-vspw = <10>;
samsung,vl-vbpd = <25>;
samsung,vl-vfpd = <10>;
samsung,vl-cmd-allow-len = <0xf>;
samsung,winid = <3>;
samsung,interface-mode = <1>;
samsung,dp-enabled = <1>;
samsung,dual-lcd-enabled = <0>;
};
};

10
arch/arm/include/asm/arch-exynos/cpu.h
View File

@ -227,6 +227,13 @@ static inline void s5p_set_cpu_id(void)
/* Exynos5420 */
s5p_cpu_id = 0x5420;
break;
case 0x422:
/*
* Exynos5800 is a variant of Exynos5420
* and has product id 0x5422
*/
s5p_cpu_id = 0x5800;
break;
}
}
@ -255,6 +262,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210)
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
IS_EXYNOS_TYPE(exynos5420, 0x5420)
IS_EXYNOS_TYPE(exynos5800, 0x5800)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
@ -265,7 +273,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
if (proid_is_exynos5420()) \
if (proid_is_exynos5420() || proid_is_exynos5800()) \
return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \

1
arch/arm/include/asm/arch-exynos/dmc.h
View File

@ -450,6 +450,7 @@ enum mem_manuf {
#define CONCONTROL_RD_FETCH_SHIFT 12
#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
#define CONCONTROL_AREF_EN_SHIFT 5
#define CONCONTROL_UPDATE_MODE (1 << 3)
/* PRECHCONFIG register field */
#define PRECHCONFIG_TP_CNT_SHIFT 24

13
arch/arm/include/asm/arch-exynos/ehci.h
View File

@ -12,6 +12,13 @@
#define CLK_24MHZ 5
#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
#define RSTCON_HOSTPHY_SWRST (0xf << 3)
#define RSTCON_SWRST (0x1 << 0)
#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
#define HOST_CTRL0_COMMONON_N (1 << 9)
#define HOST_CTRL0_SIDDQ (1 << 6)
@ -61,6 +68,12 @@ struct exynos_usb_phy {
unsigned int usbotgtune;
};
struct exynos4412_usb_phy {
unsigned int usbphyctrl;
unsigned int usbphyclk;
unsigned int usbphyrstcon;
};
/* Switch on the VBUS power. */
int board_usb_vbus_init(void);

4
arch/arm/include/asm/arch-exynos/gpio.h
View File

@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_gpio_data;
else
return exynos5_gpio_data;
@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void)
static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return EXYNOS5420_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;

7
arch/arm/include/asm/arch-exynos/power.h
View File

@ -210,6 +210,13 @@ struct exynos4_power {
unsigned int gps_alive_option;
};
struct exynos4412_power {
unsigned char res1[0x0704];
unsigned int usbhost_phy_control;
unsigned int hsic1_phy_control;
unsigned int hsic2_phy_control;
};
struct exynos5_power {
unsigned int om_stat;
unsigned char res1[0x18];

46
board/samsung/odroid/odroid.c
View File

@ -382,6 +382,22 @@ static void board_gpio_init(void)
gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
gpio_direction_input(EXYNOS4X12_GPIO_X31);
/* Blue LED (Odroid X2/U2/U3) */
gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
#ifdef CONFIG_CMD_USB
/* USB3503A Reference frequency */
gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
/* USB3503A Connect */
gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
/* USB3503A Reset */
gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
#endif
}
static int pmic_init_max77686(void)
@ -462,9 +478,39 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
.usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
#endif
#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
int board_usb_init(int index, enum usb_init_type init)
{
#ifdef CONFIG_CMD_USB
struct pmic *p_pmic;
/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
if (gd->board_type == ODROID_TYPE_U3)
gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
else
gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
/* Disconnect, Reset, Connect */
gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
/* Power off and on BUCK8 for LAN9730 */
debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
p_pmic = pmic_get("MAX77686_PMIC");
if (p_pmic && !pmic_probe(p_pmic)) {
max77686_set_buck_voltage(p_pmic, 8, 750000);
max77686_set_buck_voltage(p_pmic, 8, 3300000);
}
#endif
debug("USB_udc_probe\n");
return s3c_udc_probe(&s5pc210_otg_data);
}

16
board/samsung/smdk5420/Kconfig
View File

@ -1,3 +1,19 @@
if TARGET_PEACH_PI
config SYS_BOARD
string
default "smdk5420"
config SYS_VENDOR
string
default "samsung"
config SYS_CONFIG_NAME
string
default "peach-pi"
endif
if TARGET_PEACH_PIT
config SYS_BOARD

2
board/samsung/smdk5420/MAINTAINERS
View File

@ -6,3 +6,5 @@ F: include/configs/peach-pit.h
F: configs/peach-pit_defconfig
F: include/configs/smdk5420.h
F: configs/smdk5420_defconfig
F: include/configs/peach-pi.h
F: configs/peach-pi_defconfig

5
configs/peach-pi_defconfig Normal file
View File

@ -0,0 +1,5 @@
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_PEACH_PI=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"

169
doc/README.odroid
View File

@ -141,3 +141,172 @@ And the boot sequence is:
- boot_fit - if "Image.itb" exists
- boot_zimg - if "zImage" exists
- boot_uimg - if "uImage" exists
11. USB host support
====================
The ethernet can be accessed after starting the USB subsystem in U-Boot.
The adapter does not come with a preconfigured MAC address, and hence it needs
to be set before starting USB.
setenv usbethaddr 02:DE:AD:BE:EF:FF
Note that in this example a locally managed MAC address is chosen. Care should
be taken to make these MAC addresses unique within the same subnet.
Start the USB subsystem:
Odroid # setenv usbethaddr 02:DE:AD:BE:EF:FF
Odroid # usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 4 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
scanning usb for ethernet devices... 1 Ethernet Device(s) found
Odroid #
Automatic IP assignment:
------------------------
If the ethernet is connected to a DHCP server (router maybe with DHCP enabled),
then the below will automatically assign an ip address through DHCP.
setenv autoload no
dhcp
Odroid # setenv autoload no
Odroid # dhcp
Waiting for Ethernet connection... done.
BOOTP broadcast 1
DHCP client bound to address 192.168.1.10 (524 ms)
Odroid #
Note that this automatically sets the many IP address related variables in
U-Boot that is obtained from the DHCP server.
Odroid # printenv ipaddr netmask gatewayip dnsip
ipaddr=192.168.1.10
netmask=255.255.255.0
gatewayip=192.168.1.1
dnsip=192.168.1.1
Ping example:
The ping command can be used a test to check connectivity. In this example,
192.168.1.27 is a pingable server in the network.
Odroid # ping 192.168.1.27
Waiting for Ethernet connection... done.
Using sms0 device
host 192.168.1.27 is alive
Odroid #
Static IP assignment:
---------------------
In the case where there are no DHCP servers in the network, or you want to
set the IP address statically, it can be done by:
Odroid # setenv ipaddr 192.168.1.10
Odroid # ping 192.168.1.27
Waiting for Ethernet connection... done.
Using sms0 device
host 192.168.1.27 is alive
TFTP booting:
-------------
Say there exists a tftp server in the network with address 192.168.1.27 and
it serves a kernel image (zImage.3.17) and a DTB blob (exynos4412-odroidu3.dtb)
that needs to be loaded and booted. It can be accomplished as below:
(Assumes that you have setenv usbethaddr, and have not set autoload to no)
Odroid # setenv serverip 192.168.1.27
Odroid # tftpboot 0x40080000 zImage.3.17
Waiting for Ethernet connection... done.
Using sms0 device
TFTP from server 192.168.1.27; our IP address is 192.168.1.10
Filename 'zImage.3.17'.
Load address: 0x40080000
Loading: #################################################################
#################################################################
#################################################################
#######################
52.7 KiB/s
done
Bytes transferred = 3194200 (30bd58 hex)
Odroid # tftpboot 0x42000000 exynos4412-odroidu3.dtb
Waiting for Ethernet connection... done.
Using sms0 device
TFTP from server 192.168.1.27; our IP address is 192.168.1.10
Filename 'exynos4412-odroidu3.dtb'.
Load address: 0x42000000
Loading: ####
40 KiB/s
done
Bytes transferred = 46935 (b757 hex)
Odroid # printenv bootargs
bootargs=Please use defined boot
Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/mmcblk0p2 rootwait
Odroid # bootz 40080000 - 42000000
Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ]
## Flattened Device Tree blob at 42000000
Booting using the fdt blob at 0x42000000
Loading Device Tree to 4fff1000, end 4ffff756 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xa00
... etc ...
In the above example you can substitute 'dhcp' for 'tftpboot' as well.
USB Storage booting:
--------------------
Similarly we can use the USB storage to load the kernel image/initrd/fdt etc
and boot. For this example, there is a USB drive plugged in. It has a FAT
1st partition and an EXT 2nd partition. Using the generic FS (ls/load) makes
it even easier to work with FAT/EXT file systems.
For this example the second EXT partition is used for booting and as rootfs.
The boot files - kernel and the dtb are present in the /boot directory of the
second partition.
Odroid # usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 4 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
scanning usb for ethernet devices...
Error: sms0 address not set. <----- Note the error as usbethaddr
Warning: failed to set MAC address <----- is not set.
1 Ethernet Device(s) found
Odroid # usb part 0
Partition Map for USB device 0 -- Partition Type: DOS
Part Start Sector Num Sectors UUID Type
1 3072 263168 000c4046-01 06
2 266240 13457408 000c4046-02 83
Odroid # ls usb 0:2 /boot
<DIR> 4096 .
<DIR> 4096 ..
353 boot.scr
281 boot.txt
101420 config-3.8.13.23
2127254 initrd.img-3.8.13.23
2194825 uInitrd
2194825 uInitrd-3.8.13.23
2453112 zImage
101448 config-3.8.13.26
2127670 uInitrd-3.8.13.26
2127606 initrd.img-3.8.13.26
3194200 zImage.3.17 <--- Kernel
46935 exynos4412-odroidu3.dtb <--- DTB
Odroid # load usb 0:2 40080000 /boot/zImage.3.17
3194200 bytes read in 471 ms (6.5 MiB/s)
Odroid # load usb 0:2 42000000 /boot/exynos4412-odroidu3.dtb
46935 bytes read in 233 ms (196.3 KiB/s)
Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/sda2 rootwait
Odroid # bootz 40080000 - 42000000
Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ]
## Flattened Device Tree blob at 42000000
Booting using the fdt blob at 0x42000000
Loading Device Tree to 4fff1000, end 4ffff756 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xa00
Please refer to README.usb for additional information.

52
drivers/power/pmic/pmic_max77686.c
View File

@ -42,11 +42,30 @@ static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
return 0;
}
static int max77686_buck_volt2hex(int buck, ulong uV)
{
int hex = 0;
if (buck < 5 || buck > 9) {
debug("%s: buck %d is not supported\n", __func__, buck);
return -EINVAL;
}
hex = (uV - 750000) / 50000;
if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
return hex;
debug("%s: %ld is wrong voltage value for BUCK%d\n",
__func__, uV, buck);
return -EINVAL;
}
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
{
unsigned int val, ret, hex, adr;
if (ldo < 1 && ldo > 26) {
if (ldo < 1 || ldo > 26) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
@ -68,11 +87,38 @@ int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
return ret;
}
int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
{
unsigned int val, adr;
int hex, ret;
if (buck < 5 || buck > 9) {
printf("%s: %d is an unsupported bucket number\n",
__func__, buck);
return -EINVAL;
}
adr = max77686_buck_addr[buck] + 1;
hex = max77686_buck_volt2hex(buck, uV);
if (hex < 0)
return hex;
ret = pmic_reg_read(p, adr, &val);
if (ret)
return ret;
val &= ~MAX77686_BUCK_VOLT_MASK;
ret |= pmic_reg_write(p, adr, val | hex);
return ret;
}
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
{
unsigned int val, ret, adr, mode;
if (ldo < 1 && 26 < ldo) {
if (ldo < 1 || 26 < ldo) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
@ -157,7 +203,7 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
/* mode */
switch (opmode) {
case OPMODE_OFF:
mode = MAX77686_BUCK_MODE_OFF;
mode = MAX77686_BUCK_MODE_OFF << mode_shift;
break;
case OPMODE_STANDBY:
switch (buck) {

55
drivers/usb/host/ehci-exynos.c
View File

@ -85,15 +85,10 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
}
#endif
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct exynos_usb_phy *usb)
static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
{
u32 hsic_ctrl;
set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_FSEL_MASK |
HOST_CTRL0_COMMONON_N |
@ -150,8 +145,34 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
EHCICTRL_ENAINCR16);
}
/* Reset the EHCI host controller. */
static void reset_usb_phy(struct exynos_usb_phy *usb)
static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
{
writel(CLK_24MHZ, &usb->usbphyclk);
clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
PHYPWR_NORMAL_MASK_PHY0));
setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
udelay(10);
clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
}
static void setup_usb_phy(struct exynos_usb_phy *usb)
{
set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
if (cpu_is_exynos5())
exynos5_setup_usb_phy(usb);
else if (cpu_is_exynos4())
if (proid_is_exynos4412())
exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
usb);
}
static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
{
u32 hsic_ctrl;
@ -171,6 +192,24 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
}
static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
{
setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
PHYPWR_NORMAL_MASK_PHY0));
}
/* Reset the EHCI host controller. */
static void reset_usb_phy(struct exynos_usb_phy *usb)
{
if (cpu_is_exynos5())
exynos5_reset_usb_phy(usb);
else if (cpu_is_exynos4())
if (proid_is_exynos4412())
exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
usb);
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
}

5
include/configs/arndale.h
View File

@ -9,6 +9,9 @@
#ifndef __CONFIG_ARNDALE_H
#define __CONFIG_ARNDALE_H
#define EXYNOS_FDTFILE_SETTING \
"fdtfile=exynos5250-arndale.dtb\0"
#include "exynos5250-common.h"
/* SD/MMC configuration */
@ -17,8 +20,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CMD_EXT2
/* USB */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS

17
include/configs/exynos-common.h
View File

@ -30,9 +30,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
/* Enable fdt support */
#define CONFIG_OF_LIBFDT
/* Keep L2 Cache Disabled */
#define CONFIG_CMD_CACHE
@ -42,7 +39,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_ENV_OVERWRITE
/* Size of malloc() pool before and after relocation */
@ -61,7 +57,6 @@
#define CONFIG_EXYNOS_DWMMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
/* PWM */
@ -71,22 +66,16 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_PART
#define CONFIG_PARTITION_UUIDS
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
@ -96,4 +85,6 @@
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#include <config_distro_defaults.h>
#endif /* __CONFIG_H */

56
include/configs/exynos5-common.h
View File

@ -47,17 +47,6 @@
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_CONSOLE_MUX
#define EXYNOS_DEVICE_SETTINGS \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
EXYNOS_DEVICE_SETTINGS
#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NET
#define CONFIG_CMD_HASH
/* Thermal Management Unit */
@ -174,12 +163,6 @@
#define CONFIG_ENV_SROM_BANK 1
#endif /*CONFIG_CMD_NET*/
/* Enable PXE Support */
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PXE
#define CONFIG_MENU
#endif
/* SHA hashing */
#define CONFIG_CMD_HASH
#define CONFIG_HASH_VERIFY
@ -189,8 +172,6 @@
/* Enable Time Command */
#define CONFIG_CMD_TIME
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_GPIO
/* USB boot mode */
@ -203,4 +184,41 @@
#define CONFIG_FIT
#define CONFIG_FIT_BEST_MATCH
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#ifndef MEM_LAYOUT_ENV_SETTINGS
/* 2GB RAM, bootm size of 256M, load scripts after that */
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"kernel_addr_r=0x42000000\0" \
"fdt_addr_r=0x43000000\0" \
"ramdisk_addr_r=0x43300000\0" \
"scriptaddr=0x50000000\0" \
"pxefile_addr_r=0x51000000\0"
#endif
#ifndef EXYNOS_DEVICE_SETTINGS
#define EXYNOS_DEVICE_SETTINGS \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
#endif
#ifndef EXYNOS_FDTFILE_SETTING
#define EXYNOS_FDTFILE_SETTING
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
EXYNOS_DEVICE_SETTINGS \
EXYNOS_FDTFILE_SETTING \
MEM_LAYOUT_ENV_SETTINGS \
BOOTENV
#endif /* __CONFIG_EXYNOS5_COMMON_H */

17
include/configs/exynos5-dt-common.h
View File

@ -9,6 +9,13 @@
#ifndef __CONFIG_EXYNOS5_DT_COMMON_H
#define __CONFIG_EXYNOS5_DT_COMMON_H
/* Console configuration */
#undef EXYNOS_DEVICE_SETTINGS
#define EXYNOS_DEVICE_SETTINGS \
"stdin=serial,cros-ec-keyb\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
#include "exynos5-common.h"
/* PMIC */
@ -22,14 +29,4 @@
#define CONFIG_CMD_CROS_EC
#define CONFIG_KEYBOARD
/* Console configuration */
#undef EXYNOS_DEVICE_SETTINGS
#define EXYNOS_DEVICE_SETTINGS \
"stdin=serial,cros-ec-keyb\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
EXYNOS_DEVICE_SETTINGS
#endif

2
include/configs/exynos5250-common.h
View File

@ -29,8 +29,6 @@
#define CONFIG_SPL_TEXT_BASE 0x02023400
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
#define CONFIG_IRAM_STACK 0x02050000
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK

11
include/configs/exynos5420-common.h
View File

@ -10,6 +10,8 @@
#define __CONFIG_EXYNOS5420_H
#define CONFIG_EXYNOS5420
/* A variant of Exynos5420 (Exynos5 Family) */
#define CONFIG_EXYNOS5800
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH
@ -38,14 +40,13 @@
#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024)
#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \
"exynos5420-peach-pit exynos5420-smdk5420"
#define CONFIG_MAX_I2C_NUM 11
#define CONFIG_BOARD_REV_GPIO_COUNT 2
#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
/*
@ -54,10 +55,6 @@
*/
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 7
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
/* Miscellaneous configurable options */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"

13
include/configs/odroid.h
View File

@ -198,6 +198,19 @@
#define CONFIG_CMD_GPIO
/* USB */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
/*
* Supported Odroid boards: X3, U3
* TODO: Add Odroid X support

35
include/configs/origen.h
View File

@ -56,6 +56,10 @@
#undef CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
@ -63,7 +67,36 @@
#define COPY_BL2_FNPTR_ADDR 0x02020030
#define CONFIG_SPL_TEXT_BASE 0x02021410
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x40007000\0" \
"rdaddr=0x48000000\0" \
"kerneladdr=0x40007000\0" \
"ramdiskaddr=0x48000000\0" \
"console=ttySAC2,115200n8\0" \
"mmcdev=0\0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0"
#define CONFIG_BOOTCOMMAND \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run loadbootscript; then " \
"run bootscript; " \
"fi; " \
"fi;" \
"load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
#define CONFIG_IDENT_STRING " for ORIGEN"

50
include/configs/peach-pi.h Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (C) 2014 Samsung Electronics
*
* Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_PEACH_PI_H
#define __CONFIG_PEACH_PI_H
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (0x4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
#include <configs/exynos5420-common.h>
#include <configs/exynos5-dt-common.h>
#define CONFIG_BOARD_COMMON
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_SYS_PROMPT "Peach-Pi # "
#define CONFIG_IDENT_STRING " for Peach-Pi"
#define CONFIG_VIDEO_PARADE
/* Display */
#define CONFIG_LCD
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
#define LCD_BPP LCD_COLOR16
#endif
#define CONFIG_POWER_TPS65090_EC
#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
#define CONFIG_DM_CROS_EC
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_EXYNOS
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 7
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#endif /* __CONFIG_PEACH_PI_H */

8
include/configs/peach-pit.h
View File

@ -23,8 +23,8 @@
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_SYS_PROMPT "Peach # "
#define CONFIG_IDENT_STRING " for Peach"
#define CONFIG_SYS_PROMPT "Peach-Pit # "
#define CONFIG_IDENT_STRING " for Peach-Pit"
#define CONFIG_VIDEO_PARADE
@ -43,4 +43,8 @@
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_EXYNOS
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#endif /* __CONFIG_PEACH_PIT_H */

2
include/configs/smdk2410.h
View File

@ -23,6 +23,8 @@
#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* input clock of PLL (the SMDK2410 has 12MHz input clock) */

4
include/configs/smdk5420.h
View File

@ -23,4 +23,8 @@
#define CONFIG_IDENT_STRING " for SMDK5420"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 7
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#endif /* __CONFIG_SMDK5420_H */

3
include/power/max77686_pmic.h
View File

@ -150,6 +150,7 @@ enum {
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
@ -159,6 +160,8 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
#define MAX77686_LDO_MODE_LPM (0x02 << 0x06)
#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
#define MAX77686_BUCK_VOLT_MAX_HEX 0x3f
#define MAX77686_BUCK_VOLT_MASK 0x3f
#define MAX77686_BUCK_MODE_MASK 0x03
#define MAX77686_BUCK_MODE_SHIFT_1 0x00
#define MAX77686_BUCK_MODE_SHIFT_2 0x04