arm: uniphier: use DM_TIMER of arm a9 global timer
All uniphier v7 SoCs have cortex-a9 and use cortex-a9 global timer
in a simple implementation. Now DM_TIMER of it is available
on 35751c7f3f
("timer: sti: convert sti-timer to arm a9 global timer"),
so let's switch to it.
The old driver reads the lower 32bits of counter field
and sets the prescaler as 50 with PERIPHCLK(=50MHz),
so the global timer works as a 32-bit 1MHz timer.
The DM_TIMER uses the whole 64bits with no prescaler,
so the global timer works as a 64-bit PERIPHCLK timer.
CONFIG_SYS_HZ_CLOCK is set as the default PERIPHCLK frequency,
if there is no 'clocks' property in devicetree.
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
This commit is contained in:
parent
ef75d482aa
commit
872413bb0a
@ -2,6 +2,10 @@
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soc {
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soc {
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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timer@60000200 {
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u-boot,dm-pre-reloc;
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};
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serial@54006800 {
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serial@54006800 {
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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};
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};
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@ -12,6 +12,7 @@ config ARCH_UNIPHIER_V7_MULTI
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select ARMV7_NONSEC
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select ARMV7_NONSEC
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select CPU_V7A
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_NONSEC
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select ARM_GLOBAL_TIMER if TIMER
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config ARCH_UNIPHIER_V8_MULTI
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config ARCH_UNIPHIER_V8_MULTI
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bool "UniPhier V8 SoCs"
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bool "UniPhier V8 SoCs"
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@ -8,5 +8,3 @@ obj-y += late_lowlevel_init.o
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obj-y += cache-uniphier.o
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obj-y += cache-uniphier.o
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obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o
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obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o
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endif
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endif
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obj-y += timer.o
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@ -1,39 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <config.h>
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#include <init.h>
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#include <linux/io.h>
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#include "arm-mpcore.h"
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#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
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#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1)
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static void *get_global_timer_base(void)
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{
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void *val;
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory");
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return val + GLOBAL_TIMER_OFFSET;
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}
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unsigned long timer_read_counter(void)
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{
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/*
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* ARM 64bit Global Timer is too much for our purpose.
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* We use only lower 32 bit of the timer counter.
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*/
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return readl(get_global_timer_base() + GTIMER_CNT_L);
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}
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int timer_init(void)
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{
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/* enable timer */
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writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL);
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return 0;
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}
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@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x85000000
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000
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CONFIG_SYS_MONITOR_LEN=2097152
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CONFIG_SYS_MONITOR_LEN=2097152
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CONFIG_TIMER=y
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CONFIG_SPL_TIMER=y
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CONFIG_TIMESTAMP=y
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CONFIG_TIMESTAMP=y
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
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CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
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@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x85000000
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000
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CONFIG_SYS_MONITOR_LEN=2097152
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CONFIG_SYS_MONITOR_LEN=2097152
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CONFIG_TIMER=y
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CONFIG_SPL_TIMER=y
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CONFIG_TIMESTAMP=y
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CONFIG_TIMESTAMP=y
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
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CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
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@ -36,8 +36,7 @@
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BOOT_TARGET_DEVICE_USB(func)
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BOOT_TARGET_DEVICE_USB(func)
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#if !defined(CONFIG_ARM64)
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#if !defined(CONFIG_ARM64)
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/* Time clock 1MHz */
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#define CFG_SYS_HZ_CLOCK 50000000
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#define CFG_SYS_TIMER_RATE 1000000
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#endif
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#endif
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#define CFG_SYS_NAND_REGS_BASE 0x68100000
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#define CFG_SYS_NAND_REGS_BASE 0x68100000
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