net: sh-eth: Add support R8A7790
R8A7790 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7790. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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@ -4,6 +4,7 @@
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* Copyright (C) 2008, 2011 Renesas Solutions Corp.
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* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -409,6 +410,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
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sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
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#elif defined(CONFIG_R8A7790)
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sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
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#endif
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/* Configure phy */
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ret = sh_eth_phy_config(eth);
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@ -432,7 +435,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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sh_eth_write(eth, GECMR_100B, GECMR);
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#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
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sh_eth_write(eth, 1, RTRATE);
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#elif defined(CONFIG_CPU_SH7724)
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#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790)
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val = ECMR_RTM;
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#endif
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} else if (phy->speed == 10) {
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@ -166,6 +166,7 @@ enum {
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TLFRCR,
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CERCR,
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CEECR,
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RMIIMR, /* R8A7790 */
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MAFCR,
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RTRATE,
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CSMR,
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@ -272,6 +273,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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[RMCR] = 0x0058,
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[TFUCR] = 0x0064,
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[RFOCR] = 0x0068,
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[RMIIMR] = 0x006C,
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[FCFTR] = 0x0070,
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[RPADIR] = 0x0078,
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[TRIMD] = 0x007c,
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@ -299,6 +301,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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#elif defined(CONFIG_R8A7740)
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#define SH_ETH_TYPE_GETHER
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#define BASE_IO_ADDR 0xE9A00000
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#elif defined(CONFIG_R8A7790)
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#define SH_ETH_TYPE_ETHER
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#define BASE_IO_ADDR 0xEE700200
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#endif
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/*
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@ -502,6 +507,8 @@ enum FELIC_MODE_BIT {
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ECMR_PRM = 0x00000001,
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#ifdef CONFIG_CPU_SH7724
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ECMR_RTM = 0x00000010,
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#elif defined(CONFIG_R8A7790)
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ECMR_RTM = 0x00000004,
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#endif
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};
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