Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-boot

- Add various STM32MP1 fixes for serial, env, clk, board, i2c ... - Add STM32MP1 DDR driver update: These update introduce the DDR interactive mode described in: https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode This mode is used by the CubeMX: DDR tuning tool. https://wiki.st.com/stm32mpu/index.php/STM32CubeMX The DDR interactive mode is NOT activated by default because it increase the SPL size and slow down the boot time (200ms wait added).
2019-05-24 08:13:27 -04:00
parent afe9e1f197 187c41d783
commit 866a78dc28
32 changed files with 4307 additions and 259 deletions
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1488,6 +1488,7 @@ config ARCH_STM32MP
 	imply CMD_DM
 	imply CMD_POWEROFF
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
+	imply USE_PREBOOT
 	help
 	  Support for STM32MP SoC family developed by STMicroelectronics,
 	  MPUs based on ARM cortex A core
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -49,6 +49,9 @@ unsigned long long get_ticks(void)

 ulong timer_get_boot_us(void)
 {
+	if (!gd->arch.timer_rate_hz)
+		timer_init();
+
 	return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000);
 }

--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -16,8 +16,8 @@
 * address mapping : RBC
 * Tc > + 85C : N
 */
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.43"
-#define DDR_MEM_SPEED 533
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44"
+#define DDR_MEM_SPEED 533000
 #define DDR_MEM_SIZE 0x20000000

 #define DDR_MSTR 0x00041401
@@ -108,11 +108,11 @@
 #define DDR_DX1DLLCR 0x40000000
 #define DDR_DX1DQTR 0xFFFFFFFF
 #define DDR_DX1DQSTR 0x3DB02000
-#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2GCR 0x0000CE80
 #define DDR_DX2DLLCR 0x40000000
 #define DDR_DX2DQTR 0xFFFFFFFF
 #define DDR_DX2DQSTR 0x3DB02000
-#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3GCR 0x0000CE80
 #define DDR_DX3DLLCR 0x40000000
 #define DDR_DX3DQTR 0xFFFFFFFF
 #define DDR_DX3DQSTR 0x3DB02000
--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -1,9 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-/* STM32MP157C ED1 and ED2 BOARD configuration
+ *
+ * STM32MP157C ED1 BOARD configuration
 * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
 * Reference used NT5CC256M16DP-DI from NANYA
 *
@@ -15,10 +14,11 @@
 * timing mode	optimized
 * Scheduling/QoS options : type = 2
 * address mapping : RBC
+ * Tc > + 85C : N
 */

-#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
-#define DDR_MEM_SPEED 533
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44"
+#define DDR_MEM_SPEED 533000
 #define DDR_MEM_SIZE 0x40000000

 #define DDR_MSTR 0x00040401
@@ -62,7 +62,7 @@
 #define DDR_ADDRMAP11 0x00000000
 #define DDR_ODTCFG 0x06000600
 #define DDR_ODTMAP 0x00000001
-#define DDR_SCHED 0x00001201
+#define DDR_SCHED 0x00000C01
 #define DDR_SCHED1 0x00000000
 #define DDR_PERFHPR1 0x01000001
 #define DDR_PERFLPR1 0x08000200
@@ -74,15 +74,15 @@
 #define DDR_PCCFG 0x00000010
 #define DDR_PCFGR_0 0x00010000
 #define DDR_PCFGW_0 0x00000000
-#define DDR_PCFGQOS0_0 0x02100B03
+#define DDR_PCFGQOS0_0 0x02100C03
 #define DDR_PCFGQOS1_0 0x00800100
-#define DDR_PCFGWQOS0_0 0x01100B03
+#define DDR_PCFGWQOS0_0 0x01100C03
 #define DDR_PCFGWQOS1_0 0x01000200
 #define DDR_PCFGR_1 0x00010000
 #define DDR_PCFGW_1 0x00000000
-#define DDR_PCFGQOS0_1 0x02100B03
-#define DDR_PCFGQOS1_1 0x00800100
-#define DDR_PCFGWQOS0_1 0x01100B03
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
 #define DDR_PCFGWQOS1_1 0x01000200
 #define DDR_PGCR 0x01442E02
 #define DDR_PTR0 0x0022AA5B
@@ -100,7 +100,7 @@
 #define DDR_MR2 0x00000208
 #define DDR_MR3 0x00000000
 #define DDR_ODTCR 0x00010000
-#define DDR_ZQ0CR1 0x0000005B
+#define DDR_ZQ0CR1 0x00000038
 #define DDR_DX0GCR 0x0000CE81
 #define DDR_DX0DLLCR 0x40000000
 #define DDR_DX0DQTR 0xFFFFFFFF
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -17,12 +17,20 @@ config SPL
 	select SPL_DM_RESET
 	select SPL_SERIAL_SUPPORT
 	select SPL_SYSCON
+	imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
+	imply SPL_BOOTSTAGE if BOOTSTAGE
 	imply SPL_DISPLAY_PRINT
 	imply SPL_LIBDISK_SUPPORT

 config SYS_SOC
 	default "stm32mp"

+config SYS_MALLOC_LEN
+	default 0x2000000
+
+config ENV_SIZE
+	default 0x1000
+
 config TARGET_STM32MP1
 	bool "Support stm32mp1xx"
 	select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
@@ -33,6 +41,10 @@ config TARGET_STM32MP1
 	select STM32_RCC
 	select STM32_RESET
 	select SYS_ARCH_TIMER
+	imply BOOTCOUNT_LIMIT
+	imply BOOTSTAGE
+	imply CMD_BOOTCOUNT
+	imply CMD_BOOTSTAGE
 	imply SYSRESET_PSCI if STM32MP1_TRUSTED
 	imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
 	help
@@ -70,6 +82,18 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
 	  Partition on the second MMC to load U-Boot from when the MMC is being
 	  used in raw mode

+config BOOTSTAGE_STASH_ADDR
+	default 0xC3000000
+
+if BOOTCOUNT_LIMIT
+config SYS_BOOTCOUNT_SINGLEWORD
+	default y
+
+# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
+config SYS_BOOTCOUNT_ADDR
+	default 0x5C00A154
+endif
+
 if DEBUG_UART

 config DEBUG_UART_BOARD_INIT
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -7,9 +7,9 @@
 #include <dm.h>
 #include <misc.h>
 #include <asm/io.h>
-#include <linux/iopoll.h>
 #include <asm/arch/stm32mp1_smc.h>
 #include <linux/arm-smccc.h>
+#include <linux/iopoll.h>

 #define BSEC_OTP_MAX_VALUE		95

--- a/arch/arm/mach-stm32mp/include/mach/ddr.h
+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h
@@ -6,6 +6,13 @@
 #ifndef __MACH_STM32MP_DDR_H_
 #define __MACH_STM32MP_DDR_H_

-int board_ddr_power_init(void);
+/* DDR power initializations */
+enum ddr_type {
+	STM32MP_DDR3,
+	STM32MP_LPDDR2,
+	STM32MP_LPDDR3,
+};
+
+int board_ddr_power_init(enum ddr_type ddr_type);

 #endif
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -88,6 +88,7 @@ enum boot_device {
 #define TAMP_BACKUP_MAGIC_NUMBER	TAMP_BACKUP_REGISTER(4)
 #define TAMP_BACKUP_BRANCH_ADDRESS	TAMP_BACKUP_REGISTER(5)
 #define TAMP_BOOT_CONTEXT		TAMP_BACKUP_REGISTER(20)
+#define TAMP_BOOTCOUNT			TAMP_BACKUP_REGISTER(21)

 #define TAMP_BOOT_MODE_MASK		GENMASK(15, 8)
 #define TAMP_BOOT_MODE_SHIFT		8
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -47,14 +47,14 @@ static u32 __secure stm32mp_get_gicd_base_address(void)
 	return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
 }

-static void __secure stm32mp_smp_kick_all_cpus(void)
+static void __secure stm32mp_raise_sgi0(int cpu)
 {
 	u32 gic_dist_addr;

 	gic_dist_addr = stm32mp_get_gicd_base_address();

-	/* kick all CPUs (except this one) by writing to GICD_SGIR */
-	writel(1U << 24, gic_dist_addr + GICD_SGIR);
+	/* ask cpu with SGI0 */
+	writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
 }

 void __secure psci_arch_cpu_entry(void)
@@ -62,6 +62,9 @@ void __secure psci_arch_cpu_entry(void)
 	u32 cpu = psci_get_cpu_id();

 	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
+
+	/* reset magic in TAMP register */
+	writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
 }

 int __secure psci_features(u32 function_id, u32 psci_fid)
@@ -127,6 +130,16 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
 	if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
 		return ARM_PSCI_RET_ALREADY_ON;

+	/* reset magic in TAMP register */
+	if (readl(TAMP_BACKUP_MAGIC_NUMBER))
+		writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
+	/*
+	 * ROM code need a first SGI0 after core reset
+	 * core is ready when magic is set to 0 in ROM code
+	 */
+	while (readl(TAMP_BACKUP_MAGIC_NUMBER))
+		stm32mp_raise_sgi0(cpu);
+
 	/* store target PC and context id*/
 	psci_save(cpu, pc, context_id);

@@ -142,7 +155,8 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
 		writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
 		       TAMP_BACKUP_MAGIC_NUMBER);

-	stm32mp_smp_kick_all_cpus();
+	/* Generate an IT to start the core */
+	stm32mp_raise_sgi0(cpu);

 	return ARM_PSCI_RET_SUCCESS;
 }