diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 0c166fd6c9..520cb90280 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -27,8 +27,8 @@ #include #include #include -#include #include +#include #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -218,27 +218,10 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev) } #endif -int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { - static const char *fsl_phy_enet_if_str[] = { - [MII] = "mii", - [RMII] = "rmii", - [GMII] = "gmii", - [RGMII] = "rgmii", - [RGMII_ID] = "rgmii-id", - [RGMII_RXID] = "rgmii-rxid", - [SGMII] = "sgmii", - [TBI] = "tbi", - [RTBI] = "rtbi", - [XAUI] = "xgmii", - [FSL_ETH_IF_NONE] = "", - }; - - if (phyc > ARRAY_SIZE(fsl_phy_enet_if_str)) - return fdt_setprop_string(blob, offset, "phy-connection-type", ""); - return fdt_setprop_string(blob, offset, "phy-connection-type", - fsl_phy_enet_if_str[phyc]); + phy_string_for_interface(phyc)); } #ifdef CONFIG_SYS_SRIO diff --git a/arch/powerpc/include/asm/fsl_enet.h b/arch/powerpc/include/asm/fsl_enet.h index 1f8f8e493f..8227b667cb 100644 --- a/arch/powerpc/include/asm/fsl_enet.h +++ b/arch/powerpc/include/asm/fsl_enet.h @@ -13,20 +13,7 @@ #ifndef __ASM_PPC_FSL_ENET_H #define __ASM_PPC_FSL_ENET_H -enum fsl_phy_enet_if { - MII, - RMII, - GMII, - RGMII, - RGMII_ID, - RGMII_RXID, - RGMII_TXID, - SGMII, - TBI, - RTBI, - XAUI, - FSL_ETH_IF_NONE, -}; +#include struct tsec_mii_mng { u32 miimcfg; /* MII management configuration reg */ @@ -38,6 +25,6 @@ struct tsec_mii_mng { u32 ifstat; /* Interface Status Register */ } __attribute__ ((packed)); -int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc); +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); #endif /* __ASM_PPC_FSL_ENET_H */ diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 0babd2648a..51d8035203 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -16,6 +16,7 @@ #include #include #include +#include #if defined(CONFIG_PCI) #include #endif @@ -160,8 +161,9 @@ int board_eth_init(bd_t *bd) int i; for (i = 0; i < ARRAY_SIZE(uec_info); i++) - uec_info[i].enet_interface_type = RGMII_RXID; - uec_info[i].speed = 1000; + uec_info[i].enet_interface_type = + PHY_INTERFACE_MODE_RGMII_RXID; + uec_info[i].speed = SPEED_1000; } return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); } @@ -398,7 +400,7 @@ void ft_board_setup(void *blob, bd_t *bd) "phy-connection-type", 0); if (prop && (strcmp(prop, "rgmii-id") == 0)) fdt_fixup_phy_connection(blob, path, - RGMII_RXID); + PHY_INTERFACE_MODE_RGMII_RXID); } #endif #if defined(CONFIG_HAS_ETH1) @@ -410,7 +412,7 @@ void ft_board_setup(void *blob, bd_t *bd) "phy-connection-type", 0); if (prop && (strcmp(prop, "rgmii-id") == 0)) fdt_fixup_phy_connection(blob, path, - RGMII_RXID); + PHY_INTERFACE_MODE_RGMII_RXID); } #endif } diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index ee1ebd98ba..650a4fe483 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "pci.h" #include "../common/pq-mds-pib.h" @@ -155,7 +156,7 @@ static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias, return; } - err = fdt_fixup_phy_connection(blob, off, SGMII); + err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII); if (err) { printf("WARNING: could not set phy-connection-type for %s: " diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index ecda222990..89557d221f 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -39,6 +39,7 @@ #include #include #include +#include #include "bcsr.h" #if defined(CONFIG_PQ_MDS_PIB) @@ -550,7 +551,8 @@ void ft_board_setup(void *blob, bd_t *bd) break; } - err = fdt_fixup_phy_connection(blob, nodeoff, RMII); + err = fdt_fixup_phy_connection(blob, nodeoff, + PHY_INTERFACE_MODE_RMII); if (err < 0) { printf("WARNING: could not set phy-connection-type " diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index cd80f83522..1ecb1379a5 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -30,6 +30,7 @@ #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#include /* Default UTBIPAR SMI address */ #ifndef CONFIG_UTBIPAR_INIT_TBIPA @@ -321,9 +322,9 @@ static int uec_set_mac_duplex(uec_private_t *uec, int duplex) } static int uec_set_mac_if_mode(uec_private_t *uec, - enum fsl_phy_enet_if if_mode, int speed) + phy_interface_t if_mode, int speed) { - enum fsl_phy_enet_if enet_if_mode; + phy_interface_t enet_if_mode; uec_info_t *uec_info; uec_t *uec_regs; u32 upsmr; @@ -345,15 +346,15 @@ static int uec_set_mac_if_mode(uec_private_t *uec, upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); switch (speed) { - case 10: + case SPEED_10: maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; switch (enet_if_mode) { - case MII: + case PHY_INTERFACE_MODE_MII: break; - case RGMII: + case PHY_INTERFACE_MODE_RGMII: upsmr |= (UPSMR_RPM | UPSMR_R10M); break; - case RMII: + case PHY_INTERFACE_MODE_RMII: upsmr |= (UPSMR_R10M | UPSMR_RMM); break; default: @@ -361,15 +362,15 @@ static int uec_set_mac_if_mode(uec_private_t *uec, break; } break; - case 100: + case SPEED_100: maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; switch (enet_if_mode) { - case MII: + case PHY_INTERFACE_MODE_MII: break; - case RGMII: + case PHY_INTERFACE_MODE_RGMII: upsmr |= UPSMR_RPM; break; - case RMII: + case PHY_INTERFACE_MODE_RMII: upsmr |= UPSMR_RMM; break; default: @@ -377,23 +378,24 @@ static int uec_set_mac_if_mode(uec_private_t *uec, break; } break; - case 1000: + case SPEED_1000: maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; switch (enet_if_mode) { - case GMII: + case PHY_INTERFACE_MODE_GMII: break; - case TBI: + case PHY_INTERFACE_MODE_TBI: upsmr |= UPSMR_TBIM; break; - case RTBI: + case PHY_INTERFACE_MODE_RTBI: upsmr |= (UPSMR_RPM | UPSMR_TBIM); break; - case RGMII_RXID: - case RGMII_ID: - case RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII: upsmr |= UPSMR_RPM; break; - case SGMII: + case PHY_INTERFACE_MODE_SGMII: upsmr |= UPSMR_SGMM; break; default: @@ -518,7 +520,7 @@ static void adjust_link(struct eth_device *dev) struct uec_mii_info *mii_info = uec->mii_info; extern void change_phy_interface_mode(struct eth_device *dev, - enum fsl_phy_enet_if mode, int speed); + phy_interface_t mode, int speed); uec_regs = uec->uec_regs; if (mii_info->link) { @@ -536,19 +538,19 @@ static void adjust_link(struct eth_device *dev) } if (mii_info->speed != uec->oldspeed) { - enum fsl_phy_enet_if mode = \ + phy_interface_t mode = uec->uec_info->enet_interface_type; if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { switch (mii_info->speed) { - case 1000: + case SPEED_1000: break; - case 100: + case SPEED_100: printf ("switching to rgmii 100\n"); - mode = RGMII; + mode = PHY_INTERFACE_MODE_RGMII; break; - case 10: + case SPEED_10: printf ("switching to rgmii 10\n"); - mode = RGMII; + mode = PHY_INTERFACE_MODE_RGMII; break; default: printf("%s: Ack,Speed(%d)is illegal\n", @@ -1112,8 +1114,8 @@ static int uec_startup(uec_private_t *uec) out_be32(&uec_regs->utbipar, utbipar); /* Configure the TBI for SGMII operation */ - if ((uec->uec_info->enet_interface_type == SGMII) && - (uec->uec_info->speed == 1000)) { + if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) && + (uec->uec_info->speed == SPEED_1000)) { uec_write_phy_reg(uec->dev, uec_regs->utbipar, ENET_TBI_MII_ANA, TBIANA_SETTINGS); diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 94eb9a26d7..e63bf3a652 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -25,6 +25,7 @@ #include "qe.h" #include "uccf.h" +#include #include #define MAX_TX_THREADS 8 @@ -691,7 +692,7 @@ typedef struct uec_info { u16 rx_bd_ring_len; u16 tx_bd_ring_len; u8 phy_address; - enum fsl_phy_enet_if enet_interface_type; + phy_interface_t enet_interface_type; int speed; } uec_info_t; diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index c83ca4b582..e26218be88 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -25,6 +25,7 @@ #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#include #define ugphy_printk(format, arg...) \ printf(format "\n", ## arg) @@ -456,8 +457,9 @@ static int bcm_init(struct uec_mii_info *mii_info) gbit_config_aneg(mii_info); - if ((uec->uec_info->enet_interface_type == RGMII_RXID) && - (uec->uec_info->speed == 1000)) { + if ((uec->uec_info->enet_interface_type == + PHY_INTERFACE_MODE_RGMII_RXID) && + (uec->uec_info->speed == SPEED_1000)) { u16 val; int cnt = 50; @@ -485,22 +487,22 @@ static int uec_marvell_init(struct uec_mii_info *mii_info) { struct eth_device *edev = mii_info->dev; uec_private_t *uec = edev->priv; - enum fsl_phy_enet_if iface = uec->uec_info->enet_interface_type; + phy_interface_t iface = uec->uec_info->enet_interface_type; int speed = uec->uec_info->speed; - if ((speed == 1000) && - (iface == RGMII_ID || - iface == RGMII_RXID || - iface == RGMII_TXID)) { + if ((speed == SPEED_1000) && + (iface == PHY_INTERFACE_MODE_RGMII_ID || + iface == PHY_INTERFACE_MODE_RGMII_RXID || + iface == PHY_INTERFACE_MODE_RGMII_TXID)) { int temp; temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR); - if (iface == RGMII_ID) { + if (iface == PHY_INTERFACE_MODE_RGMII_ID) { temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY; - } else if (iface == RGMII_RXID) { + } else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) { temp &= ~MII_M1111_TX_DELAY; temp |= MII_M1111_RX_DELAY; - } else if (iface == RGMII_TXID) { + } else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) { temp &= ~MII_M1111_RX_DELAY; temp |= MII_M1111_TX_DELAY; } @@ -853,10 +855,8 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) return theInfo; } -void marvell_phy_interface_mode (struct eth_device *dev, - enum fsl_phy_enet_if type, - int speed - ) +void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type, + int speed) { uec_private_t *uec = (uec_private_t *) dev->priv; struct uec_mii_info *mii_info; @@ -868,8 +868,8 @@ void marvell_phy_interface_mode (struct eth_device *dev, } mii_info = uec->mii_info; - if (type == RGMII) { - if (speed == 100) { + if (type == PHY_INTERFACE_MODE_RGMII) { + if (speed == SPEED_100) { uec_phy_write(mii_info, 0x00, 0x9140); uec_phy_write(mii_info, 0x1d, 0x001f); uec_phy_write(mii_info, 0x1e, 0x200c); @@ -890,7 +890,7 @@ void marvell_phy_interface_mode (struct eth_device *dev, uec_phy_write(mii_info, 0x00, 0xa100); uec_phy_write(mii_info, 0x00, 0x2100); udelay (1000000); - } else if (speed == 10) { + } else if (speed == SPEED_10) { uec_phy_write(mii_info, 0x14, 0x8e40); uec_phy_write(mii_info, 0x1b, 0x800b); uec_phy_write(mii_info, 0x14, 0x0c82); @@ -908,7 +908,7 @@ void marvell_phy_interface_mode (struct eth_device *dev, } void change_phy_interface_mode (struct eth_device *dev, - enum fsl_phy_enet_if type, int speed) + phy_interface_t type, int speed) { #ifdef CONFIG_PHY_MODE_NEED_CHANGE marvell_phy_interface_mode (dev, type, speed); diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 1191eea106..e25d5acc13 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -348,7 +348,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 4 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif @@ -360,7 +360,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index affa3a9cf8..f136a8e16a 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -361,7 +361,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 3 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif @@ -373,7 +373,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index a9599405dd..49d64a55eb 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -402,7 +402,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif @@ -414,7 +414,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index b0cdc02c1d..a4f42cf22d 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -319,7 +319,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 2 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif @@ -331,7 +331,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3674e495c5..6237b23b7e 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif @@ -346,7 +346,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif #endif /* CONFIG_QE */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 5a7e99ee64..8835ef5c91 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -385,13 +385,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH1 */ @@ -406,13 +406,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH2 */ @@ -427,13 +427,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 2 -#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ -#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH3 */ @@ -448,13 +448,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 3 -#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ -#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH4 */ @@ -468,7 +468,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC6_PHY_ADDR 4 -#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII +#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 #endif /* CONFIG_UEC_ETH6 */ @@ -481,7 +481,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC8_PHY_ADDR 6 -#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII +#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 #endif /* CONFIG_UEC_ETH8 */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 8fcadfee50..b98e6a1374 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -295,7 +295,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif