diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index b6881bf1ff..12dc03cfd0 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -12,6 +12,59 @@ config CMD_ERRATA
 	  This enables the 'errata' command which displays a list of errata
 	  work-arounds which are enabled for the current board.
 
+config FSL_PREPBL_ESDHC_BOOT_SECTOR
+	bool "Generate QorIQ pre-PBL eSDHC boot sector"
+	depends on MPC85xx
+	depends on SYS_EXTRA_OPTIONS = SDCARD
+	help
+	  With this option final image would have prepended QorIQ pre-PBL eSDHC
+	  boot sector suitable for SD card images. This boot sector instruct
+	  BootROM to configure L2 SRAM and eSDHC then load image from SD card
+	  into L2 SRAM and finally jump to image entry point.
+
+	  This is alternative to Freescale boot_format tool, but works only for
+	  SD card images and only for L2 SRAM booting. U-Boot images generated
+	  with this option should not passed to boot_format tool.
+
+	  For other configuration like booting from eSPI or configuring SDRAM
+	  please use Freescale boot_format tool without this option. See file
+	  doc/README.mpc85xx-sd-spi-boot
+
+config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
+	int "QorIQ pre-PBL eSDHC boot sector start offset"
+	depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
+	range 0 23
+	default 0
+	help
+	  QorIQ pre-PBL eSDHC boot sector may be located on one of the first
+	  24 SD card sectors. Select SD card sector on which final U-Boot
+	  image (with this boot sector) would be installed.
+
+	  By default first SD card sector (0) is used. But this may be changed
+	  to allow installing U-Boot image on some partition (with fixed start
+	  sector).
+
+	  Please note that any sector on SD card prior this boot sector must
+	  not contain ASCII "BOOT" bytes at sector offset 0x40.
+
+config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
+	int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
+	depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
+	default 1
+	range 1 8388607
+	help
+	  Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
+	  sector on which would be stored raw U-Boot image.
+
+	  By default is it second sector (1) which is the first available free
+	  sector (on the first sector is stored boot sector). It can be any
+	  sector number which offset in bytes can be expressed by 32-bit number.
+
+	  In case this final U-Boot image (with this boot sector) is put on
+	  the FAT32 partition into reserved boot area, this data sector needs
+	  to be at least 2 (third sector) because FAT32 use second sector for
+	  its data.
+
 choice
 	prompt "Target select"
 	optional
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 8a6340d800..9d44fa4158 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -57,6 +57,100 @@
 	GOT_ENTRY(__bss_start)
 	END_GOT
 
+#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+
+/* Maximal size of the image */
+#ifdef CONFIG_SPL_BUILD
+#define MAX_IMAGE_SIZE (CONFIG_SPL_MAX_SIZE - (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512))
+#else
+#define MAX_IMAGE_SIZE CONFIG_SYS_L2_SIZE
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512
+#error "CONFIG_SPL_MAX_SIZE is too small for CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA"
+#endif
+
+#if MAX_IMAGE_SIZE > CONFIG_SYS_L2_SIZE
+#error "Image is too big"
+#endif
+
+#define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
+#define ALIGN(x, a) (DIV_ROUND_UP(x, a) * (a))
+
+/* Definitions from C header file asm/immap_85xx.h */
+
+#define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
+
+#define MPC85xx_L2CTL				0x000
+#define MPC85xx_L2CTL_L2E			0x80000000
+#define MPC85xx_L2CTL_L2SRAM_ENTIRE		0x00010000
+
+#define MPC85xx_L2SRBAR0			0x100
+
+#define MPC85xx_L2ERRDIS			0xe44
+#define MPC85xx_L2ERRDIS_MBECC			0x00000008
+#define MPC85xx_L2ERRDIS_SBECC			0x00000004
+
+/* Definitions from C header file fsl_esdhc.h */
+
+#define ESDHCCTL				0x0002e40c
+#define ESDHCCTL_SNOOP				0x00000040
+
+/*
+ * QorIQ pre-PBL eSDHC boot sector:
+ * Instruct BootROM to configure L2 SRAM and eSDHC then load image
+ * from SD card into L2 SRAM and finally jump to image entry point.
+ */
+	.section .bootsect, "a"
+	.globl bootsect
+
+bootsect:
+	.org 0x40 /* BOOT signature */
+	.ascii "BOOT"
+
+	.org 0x48 /* Number of bytes to be copied, must be multiple of block size (512) */
+	.long ALIGN(MAX_IMAGE_SIZE, 512)
+
+	.org 0x50 /* Source address from the beginning of boot sector in byte address format, must be multiple of block size (512) */
+	.long (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_START + CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA) * 512
+
+	.org 0x58 /* Target address in the system's local memory address space */
+	.long CONFIG_SYS_MONITOR_BASE
+
+	.org 0x60 /* Execution starting address */
+	.long _start
+
+	.org 0x68 /* Number of configuration data pairs */
+	.long DIV_ROUND_UP(.Lconf_pair_end - .Lconf_pair_start, 8)
+
+	.org 0x80 /* Start of configuration */
+	.Lconf_pair_start:
+
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
+	.long CONFIG_SYS_INIT_L2_ADDR
+
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
+	.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
+
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
+	.long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
+
+	.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */
+	.long ESDHCCTL_SNOOP
+
+	.long 0x40000001 /* Command: Delay in 8 CCB clocks */
+	.long 256
+
+	.long 0x80000001 /* End of configuration */
+	.Lconf_pair_end:
+
+	.org 0x1b8 /* Reserved for MBR/DBR */
+	.org 0x200 /* End of boot sector */
+
+#endif
+#endif
+
 /*
  * e500 Startup -- after reset only the last 4KB of the effective
  * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 62c3c51dea..e881537452 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -12,6 +12,14 @@ OUTPUT_ARCH(powerpc)
 
 SECTIONS
 {
+/* Optional boot sector */
+#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR)
+	.bootsect IMAGE_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : {
+		KEEP(*(.bootsect))
+		. = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512;
+	}
+#endif
+
 	. = IMAGE_TEXT_BASE;
 	.text : {
 /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 8fba712655..c766f20cb0 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -16,6 +16,14 @@ ENTRY(_start)
 
 SECTIONS
 {
+  /* Optional boot sector */
+#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR) && !defined(CONFIG_SPL)
+  .bootsect CONFIG_SYS_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : {
+    KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootsect))
+    . = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512;
+  }
+#endif
+
   /* Read-only sections, merged into text segment: */
   .text      :
   {
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 56bc355d21..a71952dcf3 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -182,7 +182,7 @@ int checkboard(void)
 {
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u8 in, out, io_config, val;
+	u8 in, out, invert, io_config, val;
 	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
 
 	/* FIXME: This should just use the model from the device tree or similar */
@@ -210,6 +210,7 @@ int checkboard(void)
 
 	if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
 	    dm_i2c_read(dev, 1, &out, 1) < 0 ||
+	    dm_i2c_read(dev, 2, &invert, 1) < 0 ||
 	    dm_i2c_read(dev, 3, &io_config, 1) < 0) {
 		printf("Error reading i2c boot information!\n");
 		return 0; /* Don't want to hang() on this error */
@@ -219,13 +220,14 @@ int checkboard(void)
 
 	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
 	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
 	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
 		printf("Error reading i2c boot information!\n");
 		return 0; /* Don't want to hang() on this error */
 	}
 	#endif
 
-	val = (in & io_config) | (out & (~io_config));
+	val = ((in ^ invert) & io_config) | (out & (~io_config));
 
 	puts("rom_loc: ");
 	if (0) {
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 38843a96cb..105d9e38aa 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -90,14 +90,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif /* RAMBOOT/SPL */
 
 #ifdef CONFIG_SYS_INIT_L2_ADDR
-	/* *I*G - L2SRAM */
+	/* ***G - L2SRAM */
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1),
 #if CONFIG_SYS_L2_SIZE >= (256 << 10)
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
 		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 12, BOOKE_PAGESZ_256K, 1)
 #endif
 #endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index a0d583040c..ba04029df8 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -78,14 +78,14 @@
 
 #ifdef CONFIG_SDCARD
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MMC_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 #elif defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 #elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)