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rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

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The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Xu Ziyuan 2017-04-16 17:44:46 +08:00 committed by Simon Glass
parent 45112271ef
commit 85c91cb694
1 changed files with 8 additions and 0 deletions
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8
drivers/clk/rockchip/clk_rk3328.c
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@ -397,9 +397,11 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
switch (clk_id) {
case HCLK_SDMMC:
case SCLK_SDMMC:
con_id = 30;
break;
case HCLK_EMMC:
case SCLK_EMMC:
con_id = 32;
break;
default:
@ -423,9 +425,11 @@ static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
switch (clk_id) {
case HCLK_SDMMC:
case SCLK_SDMMC:
con_id = 30;
break;
case HCLK_EMMC:
case SCLK_EMMC:
con_id = 32;
break;
default:
@ -483,6 +487,8 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
return 0;
case HCLK_SDMMC:
case HCLK_EMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
rate = rk3328_mmc_get_clk(priv->cru, clk->id);
break;
case SCLK_I2C0:
@ -511,6 +517,8 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
return 0;
case HCLK_SDMMC:
case HCLK_EMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_I2C0: