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usb: gadget: bcm_udc_otg files

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Add the required files for the Broadcom UDC OTG interface.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
This commit is contained in:
Jiandong Zheng 2015-07-09 14:26:39 -07:00 committed by Marek Vasut
parent 05a950cf59
commit 854cbd2977
3 changed files with 80 additions and 0 deletions
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7
arch/arm/include/asm/arch-bcm281xx/sysmap.h
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@ -27,4 +27,11 @@
#define SECWD2_BASE_ADDR 0x35002f40
#define TIMER_BASE_ADDR 0x3e00d000
#define HSOTG_DCTL_OFFSET 0x00000804
#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
#endif

22
drivers/usb/gadget/bcm_udc_otg.h Normal file
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@ -0,0 +1,22 @@
/*
* Copyright 2015 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __BCM_UDC_OTG_H
#define __BCM_UDC_OTG_H
#include <common.h>
static inline void wfld_set(uintptr_t addr, uint32_t fld_val, uint32_t fld_mask)
{
writel(((readl(addr) & ~(fld_mask)) | (fld_val)), (addr));
}
static inline void wfld_clear(uintptr_t addr, uint32_t fld_mask)
{
writel((readl(addr) & ~(fld_mask)), (addr));
}
#endif

51
drivers/usb/gadget/bcm_udc_otg_phy.c Normal file
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@ -0,0 +1,51 @@
/*
* Copyright 2015 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sysmap.h>
#include <usb/s3c_udc.h>
#include "bcm_udc_otg.h"
void otg_phy_init(struct s3c_udc *dev)
{
/* set Phy to driving mode */
wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
udelay(100);
/* clear Soft Disconnect */
wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
HSOTG_DCTL_SFTDISCON_MASK);
/* invoke Reset (active low) */
wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
/* Reset needs to be asserted for 2ms */
udelay(2000);
/* release Reset */
wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
}
void otg_phy_off(struct s3c_udc *dev)
{
/* Soft Disconnect */
wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
HSOTG_DCTL_SFTDISCON_MASK,
HSOTG_DCTL_SFTDISCON_MASK);
/* set Phy to non-driving (reset) mode */
wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
}