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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini 2018-02-25 15:39:10 -05:00
commit 85447f785c
5 changed files with 58 additions and 1 deletions
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10
arch/arm/mach-rockchip/Kconfig
View File

@ -72,6 +72,16 @@ config ROCKCHIP_RK3288
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
if ROCKCHIP_RK3288
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
config TPL_TEXT_BASE
default 0xff704000
endif
config ROCKCHIP_RK3328
bool "Support Rockchip RK3328"
select ARM64

10
arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds Normal file
View File

@ -0,0 +1,10 @@
/*
* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE
#include "../../cpu/u-boot-spl.lds"

1
configs/vyasa-rk3288_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TPL_TEXT_BASE=0xff704004
CONFIG_TARGET_VYASA_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-vyasa"

19
drivers/clk/rockchip/clk_rk3368.c
View File

@ -568,12 +568,31 @@ static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *par
return -ENOENT;
}
static int rk3368_clk_enable(struct clk *clk)
{
switch (clk->id) {
case SCLK_MAC:
case SCLK_MAC_RX:
case SCLK_MAC_TX:
case SCLK_MACREF:
case SCLK_MACREF_OUT:
case ACLK_GMAC:
case PCLK_GMAC:
/* Required to successfully probe the Designware GMAC driver */
return 0;
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
return -ENOENT;
}
static struct clk_ops rk3368_clk_ops = {
.get_rate = rk3368_clk_get_rate,
.set_rate = rk3368_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3368_clk_set_parent,
#endif
.enable = rk3368_clk_enable,
};
static int rk3368_clk_probe(struct udevice *dev)

19
drivers/clk/rockchip/clk_rk3399.c
View File

@ -997,6 +997,16 @@ static int rk3399_clk_enable(struct clk *clk)
case HCLK_HOST1:
case HCLK_HOST1_ARB:
return 0;
case SCLK_MAC:
case SCLK_MAC_RX:
case SCLK_MAC_TX:
case SCLK_MACREF:
case SCLK_MACREF_OUT:
case ACLK_GMAC:
case PCLK_GMAC:
/* Required to successfully probe the Designware GMAC driver */
return 0;
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
@ -1236,6 +1246,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
ulong rate = 0;
switch (clk->id) {
case PLL_PPLL:
return PPLL_HZ;
case PCLK_RKPWM_PMU:
rate = rk3399_pwm_get_clk(priv->pmucru);
break;
@ -1257,6 +1269,13 @@ static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
ulong ret = 0;
switch (clk->id) {
case PLL_PPLL:
/*
* This has already been set up and we don't want/need
* to change it here. Accept the request though, as the
* device-tree has this in an 'assigned-clocks' list.
*/
return PPLL_HZ;
case SCLK_I2C0_PMU:
case SCLK_I2C4_PMU:
case SCLK_I2C8_PMU: