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arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error

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Add 1ms delay to avoid L3 timeout error during suspend resume.

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
This commit is contained in:
Brad Griffis 2019-04-29 09:59:29 +05:30 committed by Tom Rini
parent 82195797a4
commit 84cf295f84
1 changed files with 3 additions and 0 deletions
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arch/arm/mach-omap2/am33xx/ddr.c
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@ -138,6 +138,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
/* Enable read leveling */
writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
/* Wait 1ms because of L3 timeout error */
udelay(1000);
/*
* Enable full read and write leveling. Wait for read and write
* leveling bit to clear RDWRLVLFULL_START bit 31