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board: freescale: powerpc: add support for all RGMII modes

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Make sure all RGMII internal delay modes are covered.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Madalin Bucur
2020-11-04 15:09:17 +02:00
committed by Priyanka Jain
parent ccedd4ff8e
commit 848a2efd14
8 changed files with 55 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
board/freescale/corenet_ds/eth_hydra.c
View File

@@ -350,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt)
} }
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
fdt_status_okay_by_alias(fdt, "emi1_rgmii"); fdt_status_okay_by_alias(fdt, "emi1_rgmii");
break; break;
default: default:
@@ -449,6 +452,9 @@ int board_eth_init(struct bd_info *bis)
miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
/* /*
* If DTSEC4 is RGMII, then it's routed via via EC1 to * If DTSEC4 is RGMII, then it's routed via via EC1 to
* the first on-board RGMII port. If DTSEC5 is RGMII, * the first on-board RGMII port. If DTSEC5 is RGMII,

6
board/freescale/corenet_ds/eth_p4080.c
View File

@@ -367,6 +367,9 @@ int board_eth_init(struct bd_info *bis)
}; };
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
fm_info_set_phy_address(i, 0); fm_info_set_phy_address(i, 0);
mdio_mux[i] = EMI1_RGMII; mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i, fm_info_set_mdio(i,
@@ -434,6 +437,9 @@ int board_eth_init(struct bd_info *bis)
}; };
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
fm_info_set_phy_address(i, 0); fm_info_set_phy_address(i, 0);
mdio_mux[i] = EMI1_RGMII; mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i, fm_info_set_mdio(i,

12
board/freescale/corenet_ds/eth_superhydra.c
View File

@@ -317,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt)
} }
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
fdt_status_okay_by_alias(fdt, "hydra_rg"); fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n"); debug("Enabled MDIO node hydra_rg\n");
break; break;
@@ -353,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt)
} }
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
fdt_status_okay_by_alias(fdt, "hydra_rg"); fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n"); debug("Enabled MDIO node hydra_rg\n");
break; break;
@@ -557,6 +563,9 @@ int board_eth_init(struct bd_info *bis)
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
/* /*
* FM1 DTSEC5 is routed via EC1 to the first on-board * FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the * RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@ -704,6 +713,9 @@ int board_eth_init(struct bd_info *bis)
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
/* /*
* FM1 DTSEC5 is routed via EC1 to the first on-board * FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the * RGMII port. FM2 DTSEC5 is routed via EC2 to the

29
board/freescale/p2041rdb/eth.c
View File

@@ -81,17 +81,21 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
{ {
phy_interface_t intf = fm_info_get_enet_if(port); phy_interface_t intf = fm_info_get_enet_if(port);
char phy[16]; char phy[16];
int lane;
u8 slot;
switch (intf) {
/* The RGMII PHY is identified by the MAC connected to it */ /* The RGMII PHY is identified by the MAC connected to it */
if (intf == PHY_INTERFACE_MODE_RGMII) { case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
fdt_set_phy_handle(fdt, compat, addr, phy); fdt_set_phy_handle(fdt, compat, addr, phy);
} break;
/* The SGMII PHY is identified by the MAC connected to it */ /* The SGMII PHY is identified by the MAC connected to it */
if (intf == PHY_INTERFACE_MODE_SGMII) { case PHY_INTERFACE_MODE_SGMII:
int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
u8 slot;
if (lane < 0) if (lane < 0)
return; return;
slot = lane_to_slot[lane]; slot = lane_to_slot[lane];
@@ -106,16 +110,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ (port - FM1_DTSEC1)); + (port - FM1_DTSEC1));
fdt_set_phy_handle(fdt, compat, addr, phy); fdt_set_phy_handle(fdt, compat, addr, phy);
} }
} break;
case PHY_INTERFACE_MODE_XGMII:
if (intf == PHY_INTERFACE_MODE_XGMII) {
/* XAUI */ /* XAUI */
int lane = serdes_get_first_lane(XAUI_FM1); lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) { if (lane >= 0) {
/* The XAUI PHY is identified by the slot */ /* The XAUI PHY is identified by the slot */
sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
fdt_set_phy_handle(fdt, compat, addr, phy); fdt_set_phy_handle(fdt, compat, addr, phy);
} }
break;
default:
break;
} }
} }
#endif /* #ifdef CONFIG_FMAN_ENET */ #endif /* #ifdef CONFIG_FMAN_ENET */
@@ -169,6 +175,9 @@ int board_eth_init(struct bd_info *bis)
fm_info_set_phy_address(i, riser_phy_addr[i]); fm_info_set_phy_address(i, riser_phy_addr[i]);
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */ /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
fm_info_set_phy_address(i, i == FM1_DTSEC5 ? fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :

3
board/freescale/t102xrdb/eth_t102xrdb.c
View File

@@ -89,6 +89,9 @@ int board_eth_init(struct bd_info *bis)
interface = fm_info_get_enet_if(i); interface = fm_info_get_enet_if(i);
switch (interface) { switch (interface) {
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev); fm_info_set_mdio(i, dev);
break; break;

3
board/freescale/t104xrdb/eth.c
View File

@@ -77,6 +77,9 @@ int board_eth_init(struct bd_info *bis)
break; break;
#endif #endif
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
if (FM1_DTSEC4 == i) if (FM1_DTSEC4 == i)
phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
if (FM1_DTSEC5 == i) if (FM1_DTSEC5 == i)

3
board/freescale/t208xqds/eth_t208xqds.c
View File

@@ -765,6 +765,9 @@ int board_eth_init(struct bd_info *bis)
} }
break; break;
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
if (i == FM1_DTSEC3) if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII1; mdio_mux[i] = EMI1_RGMII1;
else if (i == FM1_DTSEC4 || FM1_DTSEC10) else if (i == FM1_DTSEC4 || FM1_DTSEC10)

3
board/freescale/t208xrdb/eth_t208xrdb.c
View File

@@ -76,6 +76,9 @@ int board_eth_init(struct bd_info *bis)
interface = fm_info_get_enet_if(i); interface = fm_info_get_enet_if(i);
switch (interface) { switch (interface) {
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev); fm_info_set_mdio(i, dev);
break; break;