drivers: misc: add Gateworks System Controller driver
Add a driver for the Gateworks System Controller used on Gateworks boards which provides a boot watchdog, power control, temperature monitor, and voltage ADCs. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tim Harvey
Stefano Babic
parent
6bec6c169f
commit
8479b9e6c9
@ -882,6 +882,12 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
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F: drivers/watchdog/sp805_wdt.c
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F: drivers/watchdog/sp805_wdt.c
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F: drivers/watchdog/sbsa_gwdt.c
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F: drivers/watchdog/sbsa_gwdt.c
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GATEWORKS_SC
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M: Tim Harvey <tharvey@gateworks.com>
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S: Maintained
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F: drivers/misc/gsc.c
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F: include/gsc.h
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I2C
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I2C
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M: Heiko Schocher <hs@denx.de>
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M: Heiko Schocher <hs@denx.de>
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S: Maintained
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S: Maintained
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@ -46,6 +46,14 @@ config ATSHA204A
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CryptoAuthentication module found for example on the Turris Omnia
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CryptoAuthentication module found for example on the Turris Omnia
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board.
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board.
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config GATEWORKS_SC
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bool "Gateworks System Controller Support"
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depends on MISC
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help
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Enable access for the Gateworks System Controller used on Gateworks
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boards to provide a boot watchdog, power control, temperature monitor,
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voltage ADCs, and EEPROM.
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config ROCKCHIP_EFUSE
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config ROCKCHIP_EFUSE
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bool "Rockchip e-fuse support"
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bool "Rockchip e-fuse support"
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depends on MISC
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depends on MISC
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@ -38,6 +38,7 @@ obj-$(CONFIG_FSL_IIM) += fsl_iim.o
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obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
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obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
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obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
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obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
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obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o
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obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o
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obj-$(CONFIG_GATEWORKS_SC) += gsc.o
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obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
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obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
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obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
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obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
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obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
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obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
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633
drivers/misc/gsc.c
Normal file
633
drivers/misc/gsc.c
Normal file
@ -0,0 +1,633 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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#include <command.h>
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#include <gsc.h>
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#include <i2c.h>
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#include <rtc.h>
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#include <asm/unaligned.h>
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#include <linux/delay.h>
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#include <dm/device.h>
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#include <dm/device-internal.h>
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#include <dm/ofnode.h>
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#include <dm/read.h>
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#define GSC_BUSNO 0
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#define GSC_SC_ADDR 0x20
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#define GSC_HWMON_ADDR 0x29
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#define GSC_RTC_ADDR 0x68
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/* System Controller registers */
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enum {
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GSC_SC_CTRL0 = 0,
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GSC_SC_CTRL1 = 1,
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GSC_SC_TIME = 2,
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GSC_SC_TIME_ADD = 6,
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GSC_SC_STATUS = 10,
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GSC_SC_FWCRC = 12,
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GSC_SC_FWVER = 14,
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GSC_SC_WP = 15,
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GSC_SC_RST_CAUSE = 16,
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GSC_SC_THERM_PROTECT = 19,
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};
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/* System Controller Control1 bits */
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enum {
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GSC_SC_CTRL1_SLEEP_EN = 0, /* 1 = enable sleep */
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GSC_SC_CTRL1_SLEEP_ACTIVATE = 1, /* 1 = activate sleep */
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GSC_SC_CTRL1_SLEEP_ADD = 2, /* 1 = latch and add sleep time */
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GSC_SC_CTRL1_SLEEP_NOWAKEPB = 3, /* 1 = do not wake on sleep on button press */
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GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
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GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
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GSC_SC_CTRL1_BOOT_CHK = 6, /* 1 = enable alt boot check */
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GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
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};
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/* System Controller Interrupt bits */
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enum {
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GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
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GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
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GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
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GSC_SC_IRQ_GPIO = 4, /* GPIO change */
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GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
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GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
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GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
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};
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/* System Controller WP bits */
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enum {
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GSC_SC_WP_ALL = 0, /* Write Protect All EEPROM regions */
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GSC_SC_WP_BOARDINFO = 1, /* Write Protect Board Info region */
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};
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/* System Controller Reset Cause */
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enum {
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GSC_SC_RST_CAUSE_VIN = 0,
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GSC_SC_RST_CAUSE_PB = 1,
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GSC_SC_RST_CAUSE_WDT = 2,
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GSC_SC_RST_CAUSE_CPU = 3,
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GSC_SC_RST_CAUSE_TEMP_LOCAL = 4,
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GSC_SC_RST_CAUSE_TEMP_REMOTE = 5,
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GSC_SC_RST_CAUSE_SLEEP = 6,
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GSC_SC_RST_CAUSE_BOOT_WDT = 7,
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GSC_SC_RST_CAUSE_BOOT_WDT_MAN = 8,
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GSC_SC_RST_CAUSE_SOFT_PWR = 9,
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GSC_SC_RST_CAUSE_MAX = 10,
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};
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#if (IS_ENABLED(CONFIG_DM_I2C))
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struct gsc_priv {
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int gscver;
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int fwver;
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int fwcrc;
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struct udevice *hwmon;
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struct udevice *rtc;
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};
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/*
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* GSCv2 will fail to ACK an I2C transaction if it is busy, which can occur
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* during its 1HZ timer tick while reading ADC's. When this does occur,
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* it will never be busy longer than 2 back-to-back transfers so retry 3 times.
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*/
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static int gsc_i2c_read(struct udevice *dev, uint addr, u8 *buf, int len)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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int retry = (priv->gscver == 3) ? 1 : 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = dm_i2c_read(dev, addr, buf, len);
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if (!ret)
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break;
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if (ret != -EREMOTEIO)
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break;
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mdelay(10);
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}
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return ret;
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}
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static int gsc_i2c_write(struct udevice *dev, uint addr, const u8 *buf, int len)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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int retry = (priv->gscver == 3) ? 1 : 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = dm_i2c_write(dev, addr, buf, len);
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if (!ret)
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break;
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if (ret != -EREMOTEIO)
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break;
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mdelay(10);
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}
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return ret;
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}
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static struct udevice *gsc_get_dev(int busno, int slave)
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{
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struct udevice *dev, *bus;
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
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if (ret)
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return NULL;
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ret = dm_i2c_probe(bus, slave, 0, &dev);
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if (ret)
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return NULL;
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return dev;
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}
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static int gsc_thermal_get_info(struct udevice *dev, u8 *outreg, int *tmax, bool *enable)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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int ret;
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u8 reg;
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if (priv->gscver > 2 && priv->fwver > 52) {
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ret = gsc_i2c_read(dev, GSC_SC_THERM_PROTECT, ®, 1);
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if (!ret) {
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if (outreg)
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*outreg = reg;
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if (tmax) {
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*tmax = ((reg & 0xf8) >> 3) * 2;
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if (*tmax)
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*tmax += 70;
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else
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*tmax = 120;
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}
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if (enable)
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*enable = reg & 1;
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}
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} else {
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ret = -ENODEV;
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}
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return ret;
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}
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static int gsc_thermal_get_temp(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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u32 reg, mode, val;
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const char *label;
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ofnode node;
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u8 buf[2];
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ofnode_for_each_subnode(node, dev_read_subnode(dev, "adc")) {
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if (ofnode_read_u32(node, "reg", ®))
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reg = -1;
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if (ofnode_read_u32(node, "gw,mode", &mode))
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mode = -1;
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label = ofnode_read_string(node, "label");
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if ((reg == -1) || (mode == -1) || !label)
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continue;
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if (mode != 0 || strcmp(label, "temp"))
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continue;
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memset(buf, 0, sizeof(buf));
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if (!gsc_i2c_read(priv->hwmon, reg, buf, sizeof(buf))) {
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val = buf[0] | buf[1] << 8;
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if (val > 0x8000)
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val -= 0xffff;
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return val;
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}
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}
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return 0;
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}
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static void gsc_thermal_info(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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switch (priv->gscver) {
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case 2:
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printf("board_temp:%dC ", gsc_thermal_get_temp(dev) / 10);
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break;
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case 3:
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if (priv->fwver > 52) {
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bool enabled;
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int tmax;
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if (!gsc_thermal_get_info(dev, NULL, &tmax, &enabled)) {
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puts("Thermal protection:");
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if (enabled)
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printf("enabled at %dC ", tmax);
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else
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puts("disabled ");
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}
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}
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break;
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}
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}
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static void gsc_reset_info(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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static const char * const names[] = {
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"VIN",
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"PB",
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"WDT",
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"CPU",
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"TEMP_L",
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"TEMP_R",
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"SLEEP",
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"BOOT_WDT1",
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"BOOT_WDT2",
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"SOFT_PWR",
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};
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u8 reg;
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/* reset cause */
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switch (priv->gscver) {
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case 2:
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if (!gsc_i2c_read(dev, GSC_SC_STATUS, ®, 1)) {
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if (reg & BIT(GSC_SC_IRQ_WATCHDOG)) {
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puts("RST:WDT");
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reg &= ~BIT(GSC_SC_IRQ_WATCHDOG);
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gsc_i2c_write(dev, GSC_SC_STATUS, ®, 1);
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} else {
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puts("RST:VIN");
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}
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printf(" WDT:%sabled ",
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(reg & BIT(GSC_SC_CTRL1_WDEN)) ? "en" : "dis");
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}
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break;
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case 3:
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if (priv->fwver > 52 &&
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!gsc_i2c_read(dev, GSC_SC_RST_CAUSE, ®, 1)) {
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puts("RST:");
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if (reg < ARRAY_SIZE(names))
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printf("%s ", names[reg]);
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else
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printf("0x%02x ", reg);
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}
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break;
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}
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}
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/* display hardware monitor ADC channels */
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static int gsc_hwmon(struct udevice *dev)
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{
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struct gsc_priv *priv = dev_get_priv(dev);
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u32 reg, mode, val, offset;
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const char *label;
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ofnode node;
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u8 buf[2];
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u32 r[2];
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int ret;
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/* iterate over hwmon nodes */
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ofnode_for_each_subnode(node, dev_read_subnode(dev, "adc")) {
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if (ofnode_read_u32(node, "reg", ®))
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reg = -1;
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if (ofnode_read_u32(node, "gw,mode", &mode))
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mode = -1;
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label = ofnode_read_string(node, "label");
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if ((reg == -1) || (mode == -1) || !label)
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continue;
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memset(buf, 0, sizeof(buf));
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ret = gsc_i2c_read(priv->hwmon, reg, buf, sizeof(buf));
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if (ret) {
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printf("i2c error: %d\n", ret);
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continue;
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}
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val = buf[0] | buf[1] << 8;
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switch (mode) {
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case 0: /* temperature (C*10) */
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if (val > 0x8000)
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val -= 0xffff;
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printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
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break;
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case 1: /* prescaled voltage */
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if (val != 0xffff)
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printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
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break;
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case 2: /* scaled based on ref volt and resolution */
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val *= 2500;
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val /= 1 << 12;
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/* apply pre-scaler voltage divider */
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if (!ofnode_read_u32_index(node, "gw,voltage-divider-ohms", 0, &r[0]) &&
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!ofnode_read_u32_index(node, "gw,voltage-divider-ohms", 1, &r[1]) &&
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r[0] && r[1]) {
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||||||
|
val *= (r[0] + r[1]);
|
||||||
|
val /= r[1];
|
||||||
|
}
|
||||||
|
|
||||||
|
/* adjust by offset */
|
||||||
|
val += (offset / 1000);
|
||||||
|
|
||||||
|
printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gsc_banner(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct gsc_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
/* banner */
|
||||||
|
printf("GSCv%d : v%d 0x%04x ", priv->gscver, priv->fwver, priv->fwcrc);
|
||||||
|
gsc_reset_info(dev);
|
||||||
|
gsc_thermal_info(dev);
|
||||||
|
puts("\n");
|
||||||
|
|
||||||
|
/* Display RTC */
|
||||||
|
if (priv->rtc) {
|
||||||
|
u8 buf[4];
|
||||||
|
time_t timestamp;
|
||||||
|
struct rtc_time tm;
|
||||||
|
|
||||||
|
if (!gsc_i2c_read(priv->rtc, 0, buf, 4)) {
|
||||||
|
timestamp = get_unaligned_le32(buf);
|
||||||
|
rtc_to_tm(timestamp, &tm);
|
||||||
|
printf("RTC : %4d-%02d-%02d %2d:%02d:%02d UTC\n",
|
||||||
|
tm.tm_year, tm.tm_mon, tm.tm_mday,
|
||||||
|
tm.tm_hour, tm.tm_min, tm.tm_sec);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gsc_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct gsc_priv *priv = dev_get_priv(dev);
|
||||||
|
u8 buf[32];
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = gsc_i2c_read(dev, 0, buf, sizeof(buf));
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GSC chip version:
|
||||||
|
* GSCv2 has 16 registers (which overlap)
|
||||||
|
* GSCv3 has 32 registers
|
||||||
|
*/
|
||||||
|
priv->gscver = memcmp(buf, buf + 16, 16) ? 3 : 2;
|
||||||
|
priv->fwver = buf[GSC_SC_FWVER];
|
||||||
|
priv->fwcrc = buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8;
|
||||||
|
priv->hwmon = gsc_get_dev(GSC_BUSNO, GSC_HWMON_ADDR);
|
||||||
|
if (priv->hwmon)
|
||||||
|
dev_set_priv(priv->hwmon, priv);
|
||||||
|
priv->rtc = gsc_get_dev(GSC_BUSNO, GSC_RTC_ADDR);
|
||||||
|
if (priv->rtc)
|
||||||
|
dev_set_priv(priv->rtc, priv);
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
gsc_banner(dev);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id gsc_ids[] = {
|
||||||
|
{ .compatible = "gw,gsc", },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(gsc) = {
|
||||||
|
.name = "gsc",
|
||||||
|
.id = UCLASS_MISC,
|
||||||
|
.of_match = gsc_ids,
|
||||||
|
.probe = gsc_probe,
|
||||||
|
.priv_auto = sizeof(struct gsc_priv),
|
||||||
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int gsc_sleep(struct udevice *dev, unsigned long secs)
|
||||||
|
{
|
||||||
|
u8 regs[4];
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
printf("GSC Sleeping for %ld seconds\n", secs);
|
||||||
|
put_unaligned_le32(secs, regs);
|
||||||
|
ret = gsc_i2c_write(dev, GSC_SC_TIME_ADD, regs, sizeof(regs));
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
ret = gsc_i2c_read(dev, GSC_SC_CTRL1, regs, 1);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
regs[0] |= BIT(GSC_SC_CTRL1_SLEEP_ADD);
|
||||||
|
ret = gsc_i2c_write(dev, GSC_SC_CTRL1, regs, 1);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
regs[0] &= ~BIT(GSC_SC_CTRL1_SLEEP_ADD);
|
||||||
|
regs[0] |= BIT(GSC_SC_CTRL1_SLEEP_EN) | BIT(GSC_SC_CTRL1_SLEEP_ACTIVATE);
|
||||||
|
ret = gsc_i2c_write(dev, GSC_SC_CTRL1, regs, 1);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
err:
|
||||||
|
printf("i2c error: %d\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gsc_wd_disable(struct udevice *dev)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
u8 reg;
|
||||||
|
|
||||||
|
ret = gsc_i2c_read(dev, GSC_SC_CTRL1, ®, 1);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
reg |= BIT(GSC_SC_CTRL1_WDDIS);
|
||||||
|
reg &= ~BIT(GSC_SC_CTRL1_BOOT_CHK);
|
||||||
|
ret = gsc_i2c_write(dev, GSC_SC_CTRL1, ®, 1);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
puts("GSC : boot watchdog disabled\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
err:
|
||||||
|
puts("i2c error");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gsc_thermal(struct udevice *dev, const char *cmd, const char *val)
|
||||||
|
{
|
||||||
|
struct gsc_priv *priv = dev_get_priv(dev);
|
||||||
|
int ret, tmax;
|
||||||
|
bool enabled;
|
||||||
|
u8 reg;
|
||||||
|
|
||||||
|
if (priv->gscver < 3 || priv->fwver < 53)
|
||||||
|
return -EINVAL;
|
||||||
|
ret = gsc_thermal_get_info(dev, ®, &tmax, &enabled);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
if (cmd && !strcmp(cmd, "enable")) {
|
||||||
|
if (val && *val) {
|
||||||
|
tmax = clamp((int)simple_strtoul(val, NULL, 0), 72, 122);
|
||||||
|
reg &= ~0xf8;
|
||||||
|
reg |= ((tmax - 70) / 2) << 3;
|
||||||
|
}
|
||||||
|
reg |= BIT(0);
|
||||||
|
gsc_i2c_write(dev, GSC_SC_THERM_PROTECT, ®, 1);
|
||||||
|
} else if (cmd && !strcmp(cmd, "disable")) {
|
||||||
|
reg &= ~BIT(0);
|
||||||
|
gsc_i2c_write(dev, GSC_SC_THERM_PROTECT, ®, 1);
|
||||||
|
} else if (cmd) {
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* show status */
|
||||||
|
gsc_thermal_info(dev);
|
||||||
|
puts("\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* override in board files to display additional board EEPROM info */
|
||||||
|
__weak void board_gsc_info(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gsc_info(struct udevice *dev)
|
||||||
|
{
|
||||||
|
gsc_banner(dev);
|
||||||
|
board_gsc_info();
|
||||||
|
}
|
||||||
|
|
||||||
|
static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
|
||||||
|
{
|
||||||
|
struct udevice *dev;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* get/probe driver */
|
||||||
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev);
|
||||||
|
if (ret)
|
||||||
|
return CMD_RET_USAGE;
|
||||||
|
if (argc < 2) {
|
||||||
|
gsc_info(dev);
|
||||||
|
return CMD_RET_SUCCESS;
|
||||||
|
} else if (strcasecmp(argv[1], "sleep") == 0) {
|
||||||
|
if (argc < 3)
|
||||||
|
return CMD_RET_USAGE;
|
||||||
|
if (!gsc_sleep(dev, dectoul(argv[2], NULL)))
|
||||||
|
return CMD_RET_SUCCESS;
|
||||||
|
} else if (strcasecmp(argv[1], "hwmon") == 0) {
|
||||||
|
if (!gsc_hwmon(dev))
|
||||||
|
return CMD_RET_SUCCESS;
|
||||||
|
} else if (strcasecmp(argv[1], "wd-disable") == 0) {
|
||||||
|
if (!gsc_wd_disable(dev))
|
||||||
|
return CMD_RET_SUCCESS;
|
||||||
|
} else if (strcasecmp(argv[1], "thermal") == 0) {
|
||||||
|
char *cmd, *val;
|
||||||
|
|
||||||
|
cmd = (argc > 2) ? argv[2] : NULL;
|
||||||
|
val = (argc > 3) ? argv[3] : NULL;
|
||||||
|
if (!gsc_thermal(dev, cmd, val))
|
||||||
|
return CMD_RET_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
return CMD_RET_USAGE;
|
||||||
|
}
|
||||||
|
|
||||||
|
U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller",
|
||||||
|
"[sleep <secs>]|[hwmon]|[wd-disable][thermal [disable|enable [temp]]]\n");
|
||||||
|
|
||||||
|
/* disable boot watchdog - useful for an SPL that wants to use falcon mode */
|
||||||
|
int gsc_boot_wd_disable(void)
|
||||||
|
{
|
||||||
|
struct udevice *dev;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* get/probe driver */
|
||||||
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev);
|
||||||
|
if (!ret)
|
||||||
|
ret = gsc_wd_disable(dev);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
# else
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GSCv2 will fail to ACK an I2C transaction if it is busy, which can occur
|
||||||
|
* during its 1HZ timer tick while reading ADC's. When this does occur,
|
||||||
|
* it will never be busy longer than 2 back-to-back transfers so retry 3 times.
|
||||||
|
*/
|
||||||
|
static int gsc_i2c_read(uint chip, uint addr, u8 *buf, int len)
|
||||||
|
{
|
||||||
|
int retry = 3;
|
||||||
|
int n = 0;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
while (n++ < retry) {
|
||||||
|
ret = i2c_read(chip, addr, 1, buf, len);
|
||||||
|
if (!ret)
|
||||||
|
break;
|
||||||
|
if (ret != -EREMOTEIO)
|
||||||
|
break;
|
||||||
|
printf("%s 0x%02x retry %d\n", __func__, addr, n);
|
||||||
|
mdelay(10);
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gsc_i2c_write(uint chip, uint addr, u8 *buf, int len)
|
||||||
|
{
|
||||||
|
int retry = 3;
|
||||||
|
int n = 0;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
while (n++ < retry) {
|
||||||
|
ret = i2c_write(chip, addr, 1, buf, len);
|
||||||
|
if (!ret)
|
||||||
|
break;
|
||||||
|
if (ret != -EREMOTEIO)
|
||||||
|
break;
|
||||||
|
printf("%s 0x%02x retry %d\n", __func__, addr, n);
|
||||||
|
mdelay(10);
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* disable boot watchdog - useful for an SPL that wants to use falcon mode */
|
||||||
|
int gsc_boot_wd_disable(void)
|
||||||
|
{
|
||||||
|
u8 buf[32];
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
i2c_set_bus_num(GSC_BUSNO);
|
||||||
|
ret = gsc_i2c_read(GSC_SC_ADDR, 0, buf, sizeof(buf));
|
||||||
|
if (!ret) {
|
||||||
|
buf[GSC_SC_CTRL1] |= BIT(GSC_SC_CTRL1_WDDIS);
|
||||||
|
ret = gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, &buf[GSC_SC_CTRL1], 1);
|
||||||
|
printf("GSCv%d: v%d 0x%04x ",
|
||||||
|
memcmp(buf, buf + 16, 16) ? 3 : 2,
|
||||||
|
buf[GSC_SC_FWVER],
|
||||||
|
buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8);
|
||||||
|
if (buf[GSC_SC_STATUS] & BIT(GSC_SC_IRQ_WATCHDOG)) {
|
||||||
|
puts("RST:WDT ");
|
||||||
|
buf[GSC_SC_STATUS] &= ~BIT(GSC_SC_IRQ_WATCHDOG);
|
||||||
|
gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, &buf[GSC_SC_STATUS], 1);
|
||||||
|
} else {
|
||||||
|
puts("RST:VIN ");
|
||||||
|
}
|
||||||
|
puts("WDT:disabled\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
21
include/gsc.h
Normal file
21
include/gsc.h
Normal file
@ -0,0 +1,21 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2022 Gateworks Corporation
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _GSC_H_
|
||||||
|
#define _GSC_H_
|
||||||
|
|
||||||
|
/*
|
||||||
|
* board_gsc_info - Display additional board info
|
||||||
|
*/
|
||||||
|
void board_gsc_info(void);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* gsc_boot_wd_disable - disable the BOOT watchdog
|
||||||
|
*
|
||||||
|
* Return: 0 on success or negative error on failure
|
||||||
|
*/
|
||||||
|
int gsc_boot_wd_disable(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue
Block a user