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arm: nuvoton: Add support for Nuvoton NPCM750 BMC

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Add basic support for the Nuvoton NPCM750 EVB (Poleg).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
2022-04-19 13:32:19 +08:00
committed by Tom Rini
parent 1739a6db54
commit 84335544ea
22 changed files with 2291 additions and 0 deletions
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8
arch/arm/Kconfig
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@@ -1004,6 +1004,12 @@ config ARCH_NEXELL
select DM
select GPIO_EXTRA_HEADER
config ARCH_NPCM
bool "Support Nuvoton SoCs"
select DM
select OF_CONTROL
imply CMD_DM
config ARCH_APPLE
bool "Apple SoCs"
select ARM64
@@ -2279,6 +2285,8 @@ source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-nexell/Kconfig"
source "arch/arm/mach-npcm/Kconfig"
source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig"

1
arch/arm/Makefile
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@@ -72,6 +72,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NEXELL) += nexell
machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OWL) += owl

1
arch/arm/dts/Makefile
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@@ -1184,6 +1184,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb
dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb

1120
arch/arm/dts/nuvoton-common-npcm7xx.dtsi Normal file
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File diff suppressed because it is too large Load Diff

405
arch/arm/dts/nuvoton-npcm750-evb.dts Normal file
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@@ -0,0 +1,405 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
// Copyright 2018 Google, Inc.
/dts-v1/;
#include "nuvoton-npcm750.dtsi"
#include "dt-bindings/gpio/gpio.h"
#include "nuvoton-npcm750-pincfg-evb.dtsi"
/ {
model = "Nuvoton npcm750 Development Board (Device Tree)";
compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
aliases {
ethernet2 = &gmac0;
ethernet3 = &gmac1;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
i2c12 = &i2c12;
i2c13 = &i2c13;
i2c14 = &i2c14;
i2c15 = &i2c15;
spi0 = &spi0;
spi1 = &spi1;
fiu0 = &fiu0;
fiu1 = &fiu3;
fiu2 = &fiux;
};
chosen {
stdout-path = &serial0;
};
memory {
device_type = "memory";
reg = <0x0 0x20000000>;
};
};
&gmac0 {
phy-mode = "rgmii-id";
status = "okay";
};
&gmac1 {
phy-mode = "rgmii-id";
status = "okay";
};
&ehci1 {
status = "okay";
};
&fiu0 {
status = "okay";
spi-nor@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-rx-bus-width = <2>;
reg = <0>;
spi-max-frequency = <5000000>;
partitions@80000000 {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bbuboot1@0 {
label = "bb-uboot-1";
reg = <0x0000000 0x80000>;
read-only;
};
bbuboot2@80000 {
label = "bb-uboot-2";
reg = <0x0080000 0x80000>;
read-only;
};
envparam@100000 {
label = "env-param";
reg = <0x0100000 0x40000>;
read-only;
};
spare@140000 {
label = "spare";
reg = <0x0140000 0xC0000>;
};
kernel@200000 {
label = "kernel";
reg = <0x0200000 0x400000>;
};
rootfs@600000 {
label = "rootfs";
reg = <0x0600000 0x700000>;
};
spare1@d00000 {
label = "spare1";
reg = <0x0D00000 0x200000>;
};
spare2@f00000 {
label = "spare2";
reg = <0x0F00000 0x200000>;
};
spare3@1100000 {
label = "spare3";
reg = <0x1100000 0x200000>;
};
spare4@1300000 {
label = "spare4";
reg = <0x1300000 0x0>;
};
};
};
};
&fiu3 {
pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
status = "okay";
spi-nor@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-rx-bus-width = <2>;
reg = <0>;
spi-max-frequency = <5000000>;
partitions@A0000000 {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
system1@0 {
label = "spi3-system1";
reg = <0x0 0x0>;
};
};
};
};
&fiux {
spix-mode;
};
&watchdog1 {
status = "okay";
};
&rng {
status = "okay";
};
&serial0 {
status = "okay";
clock-frequency = <24000000>;
};
&serial1 {
status = "okay";
};
&serial2 {
status = "okay";
};
&serial3 {
status = "okay";
};
&adc {
status = "okay";
};
&lpc_kcs {
kcs1: kcs1@0 {
status = "okay";
};
kcs2: kcs2@0 {
status = "okay";
};
kcs3: kcs3@0 {
status = "okay";
};
};
/* lm75 on SVB */
&i2c0 {
clock-frequency = <100000>;
status = "okay";
lm75@48 {
compatible = "lm75";
reg = <0x48>;
status = "okay";
};
};
/* lm75 on EB */
&i2c1 {
clock-frequency = <100000>;
status = "okay";
lm75@48 {
compatible = "lm75";
reg = <0x48>;
status = "okay";
};
};
/* tmp100 on EB */
&i2c2 {
clock-frequency = <100000>;
status = "okay";
tmp100@48 {
compatible = "tmp100";
reg = <0x48>;
status = "okay";
};
};
&i2c3 {
clock-frequency = <100000>;
status = "okay";
};
&i2c5 {
clock-frequency = <100000>;
status = "okay";
};
/* tmp100 on SVB */
&i2c6 {
clock-frequency = <100000>;
status = "okay";
tmp100@48 {
compatible = "tmp100";
reg = <0x48>;
status = "okay";
};
};
&i2c7 {
clock-frequency = <100000>;
status = "okay";
};
&i2c8 {
clock-frequency = <100000>;
status = "okay";
};
&i2c9 {
clock-frequency = <100000>;
status = "okay";
};
&i2c10 {
clock-frequency = <100000>;
status = "okay";
};
&i2c11 {
clock-frequency = <100000>;
status = "okay";
};
&i2c14 {
clock-frequency = <100000>;
status = "okay";
};
&pwm_fan {
status = "okay";
fan@0 {
reg = <0x00>;
fan-tach-ch = /bits/ 8 <0x00 0x01>;
cooling-levels = <127 255>;
};
fan@1 {
reg = <0x01>;
fan-tach-ch = /bits/ 8 <0x02 0x03>;
cooling-levels = /bits/ 8 <127 255>;
};
fan@2 {
reg = <0x02>;
fan-tach-ch = /bits/ 8 <0x04 0x05>;
cooling-levels = /bits/ 8 <127 255>;
};
fan@3 {
reg = <0x03>;
fan-tach-ch = /bits/ 8 <0x06 0x07>;
cooling-levels = /bits/ 8 <127 255>;
};
fan@4 {
reg = <0x04>;
fan-tach-ch = /bits/ 8 <0x08 0x09>;
cooling-levels = /bits/ 8 <127 255>;
};
fan@5 {
reg = <0x05>;
fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
cooling-levels = /bits/ 8 <127 255>;
};
fan@6 {
reg = <0x06>;
fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
cooling-levels = /bits/ 8 <127 255>;
};
fan@7 {
reg = <0x07>;
fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
cooling-levels = /bits/ 8 <127 255>;
};
};
&spi0 {
cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
status = "okay";
Flash@0 {
compatible = "winbond,w25q128",
"jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <5000000>;
partition@0 {
label = "spi0_spare1";
reg = <0x0000000 0x800000>;
};
partition@1 {
label = "spi0_spare2";
reg = <0x800000 0x0>;
};
};
};
&spi1 {
cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
status = "okay";
Flash@0 {
compatible = "winbond,w25q128fw",
"jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <5000000>;
partition@0 {
label = "spi1_spare1";
reg = <0x0000000 0x800000>;
};
partition@1 {
label = "spi1_spare2";
reg = <0x800000 0x0>;
};
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = < &iox1_pins
&pin8_input
&pin9_output_high
&pin10_input
&pin11_output_high
&pin16_input
&pin24_output_high
&pin25_output_low
&pin32_output_high
&jtag2_pins
&pin61_output_high
&pin62_output_high
&pin63_output_high
&lpc_pins
&pin160_input
&pin162_input
&pin168_input
&pin169_input
&pin170_input
&pin187_output_high
&pin190_input
&pin191_output_high
&pin192_output_high
&pin197_output_low
&ddc_pins
&pin218_input
&pin219_output_low
&pin220_output_low
&pin221_output_high
&pin222_input
&pin223_output_low
&spix_pins
&pin228_output_low
&pin231_output_high
&pin255_input>;
};

157
arch/arm/dts/nuvoton-npcm750-pincfg-evb.dtsi Normal file
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@@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology
/ {
pinctrl: pinctrl@f0800000 {
pin8_input: pin8-input {
pins = "GPIO8/LKGPO1";
bias-disable;
input-enable;
};
pin9_output_high: pin9-output-high {
pins = "GPIO9/LKGPO2";
bias-disable;
output-high;
};
pin10_input: pin10-input {
pins = "GPIO10/IOXHLD";
bias-disable;
input-enable;
};
pin11_output_high: pin11-output-high {
pins = "GPIO11/IOXHCK";
bias-disable;
output-high;
};
pin16_input: pin16-input {
pins = "GPIO16/LKGPO0";
bias-disable;
input-enable;
};
pin24_output_high: pin24-output-high {
pins = "GPIO24/IOXHDO";
bias-disable;
output-high;
};
pin25_output_low: pin25-output-low {
pins = "GPIO25/IOXHDI";
bias-disable;
output-low;
};
pin32_output_high: pin32-output-high {
pins = "GPIO32/nSPI0CS1";
bias-disable;
output-high;
};
pin61_output_high: pin61-output-high {
pins = "GPO61/nDTR1_BOUT1/STRAP6";
bias-disable;
output-high;
};
pin62_output_high: pin62-output-high {
pins = "GPO62/nRTST1/STRAP5";
bias-disable;
output-high;
};
pin63_output_high: pin63-output-high {
pins = "GPO63/TXD1/STRAP4";
bias-disable;
output-high;
};
pin160_input: pin160-input {
pins = "GPIO160/CLKOUT/RNGOSCOUT";
bias-disable;
input-enable;
};
pin162_input: pin162-input {
pins = "GPIO162/SERIRQ";
bias-disable;
input-enable;
};
pin168_input: pin168-input {
pins = "GPIO168/nCLKRUN/nESPIALERT";
bias-disable;
input-enable;
};
pin169_input: pin169-input {
pins = "GPIO169/nSCIPME";
bias-disable;
input-enable;
};
pin170_input: pin170-input {
pins = "GPIO170/nSMI";
bias-disable;
input-enable;
};
pin187_output_high: pin187-output-high {
pins = "GPIO187/nSPI3CS1";
bias-disable;
output-high;
};
pin190_input: pin190-input {
pins = "GPIO190/nPRD_SMI";
bias-disable;
input-enable;
};
pin191_output_high: pin191-output-high {
pins = "GPIO191";
bias-disable;
output-high;
};
pin192_output_high: pin192-output-high {
pins = "GPIO192";
bias-disable;
output-high;
};
pin197_output_low: pin197-output-low {
pins = "GPIO197/SMB0DEN";
bias-disable;
output-low;
};
pin218_input: pin218-input {
pins = "GPIO218/nWDO1";
bias-disable;
input-enable;
};
pin219_output_low: pin219-output-low {
pins = "GPIO219/nWDO2";
bias-disable;
output-low;
};
pin220_output_low: pin220-output-low {
pins = "GPIO220/SMB12SCL";
bias-disable;
output-low;
};
pin221_output_high: pin221-output-high {
pins = "GPIO221/SMB12SDA";
bias-disable;
output-high;
};
pin222_input: pin222-input {
pins = "GPIO222/SMB13SCL";
bias-disable;
input-enable;
};
pin223_output_low: pin223-output-low {
pins = "GPIO223/SMB13SDA";
bias-disable;
output-low;
};
pin228_output_low: pin228-output-low {
pins = "GPIO228/nSPIXCS1";
bias-disable;
output-low;
};
pin231_output_high: pin231-output-high {
pins = "GPIO230/SPIXD3";
bias-disable;
output-high;
};
pin255_input: pin255-input {
pins = "GPI255/DACOSEL";
bias-disable;
input-enable;
};
};
};

62
arch/arm/dts/nuvoton-npcm750.dtsi Normal file
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@@ -0,0 +1,62 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
// Copyright 2018 Google, Inc.
#include "nuvoton-common-npcm7xx.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "nuvoton,npcm750-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
clocks = <&clk NPCM7XX_CLK_CPU>;
clock-names = "clk_cpu";
reg = <0>;
next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
clocks = <&clk NPCM7XX_CLK_CPU>;
clock-names = "clk_cpu";
reg = <1>;
next-level-cache = <&l2>;
};
};
soc {
timer@3fe600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x3fe600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&clk NPCM7XX_CLK_AHB>;
};
};
ahb {
gmac1: eth@f0804000 {
device_type = "network";
compatible = "snps,dwmac";
reg = <0xf0804000 0x2000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
ethernet = <1>;
clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
clock-names = "stmmaceth", "clk_gmac";
pinctrl-names = "default";
pinctrl-0 = <&rg2_pins
&rg2mdio_pins>;
status = "disabled";
};
};
};

65
arch/arm/include/asm/arch-npcm7xx/gcr.h Normal file
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@@ -0,0 +1,65 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __NPCM750_GCR_H_
#define __NPCM750_GCR_H_
/* On-Chip POLEG NPCM750 VERSIONS */
#define POLEG_Z1 0x00A92750
#define POLEG_A1 0x04A92750
#define POLEG_NPCM750 0x00000000
#define POLEG_NPCM730 0x00300395
#define POLEG_NPCM710 0x00200380
#define PWRON_SECEN 7 /* STRAP8 */
#define NPCM_GCR_BA 0xF0800000
struct npcm_gcr {
unsigned int pdid;
unsigned int pwron;
unsigned char res1[0x4];
unsigned int mfsel1;
unsigned int mfsel2;
unsigned int miscpe;
unsigned char res2[0x20];
unsigned int spswc;
unsigned int intcr;
unsigned int intsr;
unsigned char res3[0xc];
unsigned int hifcr;
unsigned int sd1irv1;
unsigned int sd1irv2;
unsigned char res4[0x4];
unsigned int intcr2;
unsigned int mfsel3;
unsigned int srcnt;
unsigned int ressr;
unsigned int rlockr1;
unsigned int flockr1;
unsigned int dscnt;
unsigned int mdlr;
unsigned char res5[0x18];
unsigned int davclvlr;
unsigned int intcr3;
unsigned char res6[0xc];
unsigned int vsintr;
unsigned int mfsel4;
unsigned int sd2irv1;
unsigned int sd2irv2;
unsigned char res7[0x8];
unsigned int cpbpntr;
unsigned char res8[0x8];
unsigned int cpctl;
unsigned int cp2bst;
unsigned int b2cpnt;
unsigned int cppctl;
unsigned int i2csegsel;
unsigned int i2csegctl;
unsigned int vsrcr;
unsigned int mlockr;
unsigned char res9[0x4c];
unsigned int scrpad;
unsigned int usb1phyctl;
unsigned int usb2phyctl;
};
#endif

26
arch/arm/mach-npcm/Kconfig Normal file
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@@ -0,0 +1,26 @@
if ARCH_NPCM
config SYS_ARCH
default "arm"
config SYS_TEXT_BASE
default 0x8000
choice
prompt "Nuvoton SoC select"
default ARCH_NPCM7xx
config ARCH_NPCM7xx
bool "Support Nuvoton NPCM7xx SoC"
select CPU_V7A
select OF_CONTROL
select DM
help
General support for NPCM7xx BMC (Poleg).
Nuvoton NPCM7xx BMC is based on the Cortex A9.
endchoice
source "arch/arm/mach-npcm/npcm7xx/Kconfig"
endif

1
arch/arm/mach-npcm/Makefile Normal file
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@@ -0,0 +1 @@
obj-$(CONFIG_ARCH_NPCM7xx) += npcm7xx/

22
arch/arm/mach-npcm/npcm7xx/Kconfig Normal file
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@@ -0,0 +1,22 @@
if ARCH_NPCM7xx
config SYS_CPU
default "armv7"
config SYS_SOC
default "npcm7xx"
config TARGET_POLEG
bool "NPCM POLEG board"
help
poleg EVB is Nuvoton evaluation board for NPCM750 SoC,
supports general functions of Basebase Management
Controller(BMC).
config SYS_MEM_TOP_HIDE
hex "Reserved TOP memory"
default 0x03000000
source "board/nuvoton/poleg_evb/Kconfig"
endif

1
arch/arm/mach-npcm/npcm7xx/Makefile Normal file
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@@ -0,0 +1 @@
obj-$(CONFIG_TARGET_POLEG) += cpu.o l2_cache_pl310_init.o l2_cache_pl310.o

66
arch/arm/mach-npcm/npcm7xx/cpu.c Normal file
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@@ -0,0 +1,66 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2021 Nuvoton Technology Corp.
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/armv7.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
int print_cpuinfo(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
unsigned int id, mdlr;
mdlr = readl(&gcr->mdlr);
printf("CPU: ");
switch (mdlr) {
case POLEG_NPCM750:
printf("NPCM750 ");
break;
case POLEG_NPCM730:
printf("NPCM730 ");
break;
case POLEG_NPCM710:
printf("NPCM710 ");
break;
default:
printf("NPCM7XX ");
break;
}
id = readl(&gcr->pdid);
switch (id) {
case POLEG_Z1:
printf("Z1 is no supported! @ ");
break;
case POLEG_A1:
printf("A1 @ ");
break;
default:
printf("Unknown\n");
break;
}
return 0;
}
void s_init(void)
{
/* Invalidate L2 cache in lowlevel_init */
v7_outer_cache_inval_all();
}
void enable_caches(void)
{
dcache_enable();
}
void disable_caches(void)
{
dcache_disable();
}

29
arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c Normal file
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@@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2021 Nuvoton Technology Corp.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/pl310.h>
void l2_pl310_init(void);
void set_pl310_ctrl(u32 enable)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
writel(enable, &pl310->pl310_ctrl);
}
void v7_outer_cache_enable(void)
{
l2_pl310_init();
set_pl310_ctrl(1);
}
void v7_outer_cache_disable(void)
{
set_pl310_ctrl(0);
}

71
arch/arm/mach-npcm/npcm7xx/l2_cache_pl310_init.S Normal file
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@@ -0,0 +1,71 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2021 Nuvoton Technology Corp.
*/
.align 5
#include <linux/linkage.h>
#ifndef CONFIG_SYS_L2CACHE_OFF
ENTRY(l2_pl310_init)
@------------------------------------------------------------------
@ L2CC (PL310) Initialization
@------------------------------------------------------------------
@ In this example PL310 PA = VA. The memory was marked as Device memory
@ in previous stages when defining CORE0 private address space
LDR r0, =0xF03FC000 @ A9_BASE_ADDR
@ Disable L2 Cache controller just in case it is already on
LDR r1, =0x0
STR r1, [r0,#0x100]
@ Set aux cntrl
@ Way size = 32KB
@ Way = 16
LDR r1, =0x02050000
ORR r1, r1, #(1 << 29) @ Instruction prefetch enable
ORR r1, r1, #(1 << 28) @ Data prefetch enable
ORR r1, r1, #(1 << 22) @ cache replacement policy
STR r1, [r0,#0x104] @ auxilary control reg at offset 0x104
@ Set tag RAM latency
@ 1 cycle RAM write access latency
@ 1 cycle RAM read access latency
@ 1 cycle RAM setup latency
LDR r1, =0x00000000
STR r1, [r0,#0x108] @ tag ram control reg at offset 0x108
@ Set Data RAM latency
@ 1 cycle RAM write access latency
@ 2 cycles RAM read access latency
@ 1 cycle RAM setup latency
LDR r1, =0x00000000
STR r1, [r0,#0x10C] @ data ram control reg at offset 0x108
@Cache maintenance - invalidate 16 ways (0xffff) - base offset 0x77C
LDR r1, =0xFFFF
STR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
poll_invalidate:
LDR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
TST r1, #1
BNE poll_invalidate
@ Ensure L2 remains disabled for the time being
LDR r1, =0x0
STR r1, [r0,#0x100]
MRC p15, 4, r0, c15, c0, 0 @ Read periph base address
@ SCU offset from base of private peripheral space = 0x000
LDR r1, [r0, #0x0] @ Read the SCU Control Register
ORR r1, r1, #0x1 @ Set bit 0 (The Enable bit)
STR r1, [r0, #0x0] @ Write back modifed value
BX lr
ENDPROC(l2_pl310_init)
#endif