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rockchip: rk3399: update PPLL and pmu_pclk frequency

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Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Kever Yang 2016-09-23 15:57:17 +08:00 committed by Simon Glass
parent e73e5fcd84
commit 8389dcbf98
1 changed files with 2 additions and 2 deletions
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4
arch/arm/include/asm/arch-rockchip/cru_rk3399.h
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@ -64,9 +64,9 @@ check_member(rk3399_cru, sdio1_con[1], 0x594);
#define APLL_HZ (600*MHz)
#define GPLL_HZ (594*MHz)
#define CPLL_HZ (384*MHz)
#define PPLL_HZ (594*MHz)
#define PPLL_HZ (676*MHz)
#define PMU_PCLK_HZ (99*MHz)
#define PMU_PCLK_HZ (48*MHz)
#define ACLKM_CORE_HZ (300*MHz)
#define ATCLK_CORE_HZ (300*MHz)