8544ds PCIE support
PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Ed Swarthout
Andrew Fleming-AFLEMING
parent
61a21e980a
commit
837f1ba05c
@ -52,8 +52,8 @@
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*/
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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@ -214,7 +214,7 @@ law_entry:
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.long 0
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.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
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.long (CFG_PCI1_MEM_BASE>>12) & 0xfffff
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.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
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.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
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@ -22,8 +22,10 @@
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <spd.h>
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#include <miiphy.h>
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@ -51,12 +53,19 @@ int checkboard (void)
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{
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_lbc_t *lbc = &immap->im_lbc;
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volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
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if ((uint)&gur->porpllsr != 0xe00e0000) {
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printf("immap size error %x\n",&gur->porpllsr);
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}
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printf ("Board: MPC8544DS\n");
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lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
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lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
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ecm->eedr = 0xffffffff; /* Clear ecm errors */
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ecm->eeer = 0xffffffff; /* Enable ecm errors */
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return 0;
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}
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@ -118,6 +127,316 @@ testdram(void)
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}
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#endif
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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int first_free_busno=0;
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void
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pci_init_board(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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if (io_sel & 1) {
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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printf (" eTSEC1 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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printf (" eTSEC3 is in sgmii mode.\n");
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}
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#ifdef CONFIG_PCIE3
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie3_hose;
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int pcie_ep = (host_agent == 3);
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int pcie_configured = io_sel >= 1;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE3 connected to ULI as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCIE3_MEM_BASE,
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CFG_PCIE3_MEM_PHYS,
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CFG_PCIE3_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCIE3_IO_BASE,
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CFG_PCIE3_IO_PHYS,
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CFG_PCIE3_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CFG_PCIE3_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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CFG_PCIE3_MEM_BASE2,
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CFG_PCIE3_MEM_PHYS2,
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CFG_PCIE3_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf (" PCIE3 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE3: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent == 5);
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int pcie_configured = io_sel & 6;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCIE1_MEM_BASE,
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CFG_PCIE1_MEM_PHYS,
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CFG_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCIE1_IO_BASE,
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CFG_PCIE1_IO_PHYS,
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CFG_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CFG_PCIE1_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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CFG_PCIE1_MEM_BASE2,
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CFG_PCIE1_MEM_PHYS2,
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CFG_PCIE1_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE1: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie2_hose;
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int pcie_ep = (host_agent == 3);
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int pcie_configured = io_sel & 4;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCIE2_MEM_BASE,
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CFG_PCIE2_MEM_PHYS,
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CFG_PCIE2_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCIE2_IO_BASE,
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CFG_PCIE2_IO_PHYS,
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CFG_PCIE2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CFG_PCIE2_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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CFG_PCIE2_MEM_BASE2,
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CFG_PCIE2_MEM_PHYS2,
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CFG_PCIE2_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf (" PCIE2 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE2: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
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#endif
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#ifdef CONFIG_PCI1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci1_hose;
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uint pci_agent = (host_agent == 6);
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uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
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uint pci_32 = 1;
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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(uint)pci
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);
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CFG_PCIE3_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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CFG_PCIE3_MEM_BASE2,
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CFG_PCIE3_MEM_PHYS2,
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CFG_PCIE3_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf ("PCI on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCI: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
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#endif
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}
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int last_stage_init(void)
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{
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return 0;
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@ -192,6 +511,37 @@ ft_board_setup(void *blob, bd_t *bd)
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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#ifdef CONFIG_PCIE1
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
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debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
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}
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#endif
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#ifdef CONFIG_PCIE2
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
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debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
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}
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#endif
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#ifdef CONFIG_PCIE3
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
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debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
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}
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#endif
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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@ -1,6 +1,8 @@
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/*
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* MPC85xx Internal Memory Map
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*
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* Copyright 2007 Freescale Semiconductor.
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*
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* Copyright(c) 2002,2003 Motorola Inc.
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* Xianghua Xiao (x.xiao@motorola.com)
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*
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@ -1526,8 +1528,22 @@ typedef struct ccsr_rio {
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typedef struct ccsr_gur {
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uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
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uint porbmsr; /* 0xe0004 - POR boot mode status register */
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#define MPC85xx_PORBMSR_HA 0x00070000
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uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
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uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
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#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
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#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
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||||
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
|
||||
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
|
||||
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
|
||||
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
|
||||
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
|
||||
#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
|
||||
#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
|
||||
#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
|
||||
#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
|
||||
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
|
||||
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
|
||||
char res1[12];
|
||||
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
|
||||
@ -1541,6 +1557,25 @@ typedef struct ccsr_gur {
|
||||
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
|
||||
char res6[12];
|
||||
uint devdisr; /* 0xe0070 - Device disable control */
|
||||
#define MPC85xx_DEVDISR_PCI1 0x80000000
|
||||
#define MPC85xx_DEVDISR_PCI2 0x40000000
|
||||
#define MPC85xx_DEVDISR_PCIE 0x20000000
|
||||
#define MPC85xx_DEVDISR_LBC 0x08000000
|
||||
#define MPC85xx_DEVDISR_PCIE2 0x04000000
|
||||
#define MPC85xx_DEVDISR_PCIE3 0x02000000
|
||||
#define MPC85xx_DEVDISR_SEC 0x01000000
|
||||
#define MPC85xx_DEVDISR_SRIO 0x00080000
|
||||
#define MPC85xx_DEVDISR_RMSG 0x00040000
|
||||
#define MPC85xx_DEVDISR_DDR 0x00010000
|
||||
#define MPC85xx_DEVDISR_CPU 0x00008000
|
||||
#define MPC85xx_DEVDISR_TB 0x00004000
|
||||
#define MPC85xx_DEVDISR_DMA 0x00000400
|
||||
#define MPC85xx_DEVDISR_TSEC1 0x00000080
|
||||
#define MPC85xx_DEVDISR_TSEC2 0x00000040
|
||||
#define MPC85xx_DEVDISR_TSEC3 0x00000020
|
||||
#define MPC85xx_DEVDISR_TSEC4 0x00000010
|
||||
#define MPC85xx_DEVDISR_I2C 0x00000004
|
||||
#define MPC85xx_DEVDISR_DUART 0x00000002
|
||||
char res7[12];
|
||||
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
|
||||
char res8[12];
|
||||
@ -1562,7 +1597,7 @@ typedef struct ccsr_gur {
|
||||
uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
|
||||
uint res14; /* 0xe0f28 */
|
||||
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
|
||||
char res15[61651];
|
||||
char res15[61648]; /* 0xe0f30 to 0xefffff */
|
||||
} ccsr_gur_t;
|
||||
|
||||
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
|
||||
|
||||
@ -34,14 +34,14 @@
|
||||
#define CONFIG_MPC8544 1
|
||||
#define CONFIG_MPC8544DS 1
|
||||
|
||||
#undef CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#undef CONFIG_PCI1 /* PCI controller 1 */
|
||||
#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
|
||||
#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
|
||||
#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
|
||||
#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCI1 1 /* PCI controller 1 */
|
||||
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
|
||||
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
|
||||
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#undef CONFIG_DDR_DLL
|
||||
@ -52,6 +52,7 @@
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_DDR_ECC_CMD
|
||||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
|
||||
|
||||
/*
|
||||
* When initializing flash, if we cannot find the manufacturer ID,
|
||||
@ -70,7 +71,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
|
||||
@ -86,13 +87,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00400000
|
||||
#define CFG_ALT_MEMTEST
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||
|
||||
@ -344,7 +345,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_SATA_ULI5288
|
||||
#define CFG_SCSI_MAX_SCSI_ID 4
|
||||
#define CFG_SCSI_MAX_LUN 1
|
||||
#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
|
||||
#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
|
||||
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
|
||||
#endif /* SCSCI */
|
||||
|
||||
@ -354,7 +355,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
@ -365,6 +366,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
||||
#undef CONFIG_MPC85XX_FEC
|
||||
|
||||
#define CONFIG_TSEC_TBI 1 /* enable internal TBI phy */
|
||||
#define CONFIG_SGMII_RISER
|
||||
#define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c /* sgmii phy base */
|
||||
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC3_PHY_ADDR 1
|
||||
|
||||
@ -374,7 +379,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
@ -392,7 +396,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
@ -415,6 +418,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_BEDBUG
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_SCSI
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
|
||||
@ -441,10 +446,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
|
||||
@ -482,7 +487,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
|
||||
#define CONFIG_HOSTNAME 8544ds_unknown
|
||||
#define CONFIG_ROOTPATH /nfs/mpc85xx
|
||||
#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot
|
||||
#define CONFIG_BOOTFILE 8544ds/uImage.uboot
|
||||
#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
|
||||
|
||||
#define CONFIG_SERVERIP 192.168.0.1
|
||||
#define CONFIG_GATEWAYIP 192.168.0.1
|
||||
@ -491,7 +497,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
@ -499,10 +505,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define PCIE_ENV \
|
||||
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
|
||||
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
|
||||
"pcie1regs=setenv a e000a; run pciereg\0" \
|
||||
"pcie2regs=setenv a e0009; run pciereg\0" \
|
||||
"pcie3regs=setenv a e000b; run pciereg\0" \
|
||||
"pcieerr=md ${a}020 1; md ${a}e00;" \
|
||||
"pcieerr=md ${a}020 1; md ${a}e00 e;" \
|
||||
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
|
||||
"pci d.w $b.0 56 1;" \
|
||||
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
|
||||
@ -511,12 +514,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
|
||||
"pci w $b.0 130 ffffffff\0" \
|
||||
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
|
||||
"pcie1err=setenv a e000a; run pcieerr\0" \
|
||||
"pcie2err=setenv a e0009; run pcieerr\0" \
|
||||
"pcie3err=setenv a e000b; run pcieerr\0" \
|
||||
"pcie1errc=setenv a e000a; run pcieerrc\0" \
|
||||
"pcie2errc=setenv a e0009; run pcieerrc\0" \
|
||||
"pcie3errc=setenv a e000b; run pcieerrc\0"
|
||||
"pcie1regs=setenv a e000a; run pciereg\0" \
|
||||
"pcie2regs=setenv a e0009; run pciereg\0" \
|
||||
"pcie3regs=setenv a e000b; run pciereg\0" \
|
||||
"pcie1cfg=setenv b 3; run pciecfg\0" \
|
||||
"pcie2cfg=setenv b 5; run pciecfg\0" \
|
||||
"pcie3cfg=setenv b 0; run pciecfg\0" \
|
||||
"pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
|
||||
"pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
|
||||
"pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
|
||||
"pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
|
||||
"pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
|
||||
"pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
|
||||
#else
|
||||
#define PCIE_ENV ""
|
||||
#endif
|
||||
@ -524,14 +533,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#if defined(CONFIG_PCI1)
|
||||
#define PCI_ENV \
|
||||
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
|
||||
"echo e;md ${a}e00 9\0" \
|
||||
"echo e;md ${a}e00 9\0" \
|
||||
"pci1regs=setenv a e0008; run pcireg\0" \
|
||||
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
|
||||
"pci d.w $b.0 56 1\0" \
|
||||
"pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
|
||||
"pci w.w $b.0 56 ffff\0" \
|
||||
"pci1err=setenv a e0008; run pcierr\0" \
|
||||
"pci1errc=setenv a e0008; run pcierrc\0"
|
||||
"pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
|
||||
"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
|
||||
"pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
|
||||
"pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
|
||||
#else
|
||||
#define PCI_ENV ""
|
||||
#endif
|
||||
@ -551,25 +560,39 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define ENET_ENV ""
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \
|
||||
"eoi=mw e00400b0 0\0" \
|
||||
"iack=md e00400a0 1\0" \
|
||||
"ramdiskfile=8544ds/ramdisk.uboot\0" \
|
||||
"dtbaddr=c00000\0" \
|
||||
"dtbfile=8544ds/mpc8544ds.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"eoi=mw e00400b0 0\0" \
|
||||
"iack=md e00400a0 1\0" \
|
||||
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
|
||||
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
|
||||
"ddrregs=setenv a e0002; run ddrreg\0" \
|
||||
"ddrregs=setenv a e0002; run ddrreg\0" \
|
||||
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
|
||||
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
|
||||
"guregs=setenv a e00e0; run gureg\0" \
|
||||
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
|
||||
"guregs=setenv a e00e0; run gureg\0" \
|
||||
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
|
||||
"ecmregs=setenv a e0001; run ecmreg\0" \
|
||||
PCIE_ENV \
|
||||
PCI_ENV \
|
||||
"ecmregs=setenv a e0001; run ecmreg\0" \
|
||||
"lawregs=md e0000c08 4b\0" \
|
||||
"lbcregs=md e0005000 36\0" \
|
||||
"dma0regs=md e0021100 12\0" \
|
||||
"dma1regs=md e0021180 12\0" \
|
||||
"dma2regs=md e0021200 12\0" \
|
||||
"dma3regs=md e0021280 12\0" \
|
||||
PCIE_ENV \
|
||||
PCI_ENV \
|
||||
ENET_ENV
|
||||
|
||||
|
||||
@ -579,23 +602,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr - $dtbaddr"
|
||||
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $dtbaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/sda3 rw " \
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr - $dtbaddr"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user