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board: sifive: use ccache driver instead of helper function

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Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Zong Li 2021-09-01 15:01:42 +08:00 committed by Leo Yu-Chi Liang
parent 213ed175b0
commit 835210a125
10 changed files with 9 additions and 156 deletions
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2
arch/riscv/cpu/fu540/Kconfig
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@ -19,6 +19,8 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII

1
arch/riscv/cpu/fu540/Makefile
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@ -8,5 +8,4 @@ obj-y += spl.o
else
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o
endif

55
arch/riscv/cpu/fu540/cache.c
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@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
/* Register offsets */
#define L2_CACHE_CONFIG 0x000
#define L2_CACHE_ENABLE 0x008
#define MASK_NUM_WAYS GENMASK(15, 8)
#define NUM_WAYS_SHIFT 8
DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
int node;
fdt_addr_t base;
u32 config;
u32 ways;
volatile u32 *enable;
node = fdt_node_offset_by_compatible(blob, -1,
"sifive,fu540-c000-ccache");
if (node < 0)
return node;
base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
NULL, false);
if (base == FDT_ADDR_T_NONE)
return FDT_ADDR_T_NONE;
config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
/* memory barrier */
mb();
(*enable) = ways - 1;
/* memory barrier */
mb();
return 0;
}

2
arch/riscv/cpu/fu740/Kconfig
View File

@ -19,6 +19,8 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII

1
arch/riscv/cpu/fu740/Makefile
View File

@ -8,5 +8,4 @@ obj-y += spl.o
else
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o
endif

55
arch/riscv/cpu/fu740/cache.c
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@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020-2021 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <asm/global_data.h>
/* Register offsets */
#define L2_CACHE_CONFIG 0x000
#define L2_CACHE_ENABLE 0x008
#define MASK_NUM_WAYS GENMASK(15, 8)
#define NUM_WAYS_SHIFT 8
DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
int node;
fdt_addr_t base;
u32 config;
u32 ways;
volatile u32 *enable;
node = fdt_node_offset_by_compatible(blob, -1,
"sifive,fu740-c000-ccache");
if (node < 0)
return node;
base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
NULL, false);
if (base == FDT_ADDR_T_NONE)
return FDT_ADDR_T_NONE;
config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
/* memory barrier */
mb();
(*enable) = ways - 1;
/* memory barrier */
mb();
return 0;
}

14
arch/riscv/include/asm/arch-fu540/cache.h
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@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifve.com>
*/
#ifndef _CACHE_SIFIVE_H
#define _CACHE_SIFIVE_H
int cache_enable_ways(void);
#endif /* _CACHE_SIFIVE_H */

14
arch/riscv/include/asm/arch-fu740/cache.h
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@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020-2021 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifve.com>
*/
#ifndef _CACHE_SIFIVE_H
#define _CACHE_SIFIVE_H
int cache_enable_ways(void);
#endif /* _CACHE_SIFIVE_H */

10
board/sifive/unleashed/unleashed.c
View File

@ -6,6 +6,7 @@
* Anup Patel <anup.patel@wdc.com>
*/
#include <cpu_func.h>
#include <dm.h>
#include <env.h>
#include <init.h>
@ -15,7 +16,6 @@
#include <linux/delay.h>
#include <misc.h>
#include <spl.h>
#include <asm/arch/cache.h>
#include <asm/sections.h>
/*
@ -126,14 +126,8 @@ void *board_fdt_blob_setup(void)
int board_init(void)
{
int ret;
/* enable all cache ways */
ret = cache_enable_ways();
if (ret) {
debug("%s: could not enable cache ways\n", __func__);
return ret;
}
enable_caches();
return 0;
}

11
board/sifive/unmatched/unmatched.c
View File

@ -7,8 +7,8 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <asm/arch/cache.h>
#include <asm/sections.h>
void *board_fdt_blob_setup(void)
@ -23,13 +23,8 @@ void *board_fdt_blob_setup(void)
int board_init(void)
{
int ret;
/* enable all cache ways */
ret = cache_enable_ways();
if (ret) {
debug("%s: could not enable cache ways\n", __func__);
return ret;
}
enable_caches();
return 0;
}