From 5576bb36ad7954af31474b778bfe037f5ef39ec6 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 27 Jan 2022 10:31:02 +0200 Subject: [PATCH 01/11] ARM: at91: sama5d2: Enable the use of Galois Tables from ROM sama5d2 contains in its ROM memory BCH code tables for NAND Flash ECC correction. Enable the use of the GF tables defined in ROM. This should speed up the boot process, as the tables are no longer constructed at runtime. Tested with sama5d2-ptc-ek. Reported-by: David Mosberger-Tang Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/include/mach/sama5d2.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index 9d9462725c..5ff20e9573 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -129,6 +129,7 @@ /* * Address Memory Space */ +#define ATMEL_BASE_ROM 0x00000000 #define ATMEL_BASE_CS0 0x10000000 #define ATMEL_BASE_DDRCS 0x20000000 #define ATMEL_BASE_CS1 0x60000000 @@ -141,6 +142,12 @@ #define ATMEL_BASE_QSPI0_MEM 0xd0000000 #define ATMEL_BASE_QSPI1_MEM 0xd8000000 +/* + * PMECC tables in ROM + */ +#define ATMEL_PMECC_INDEX_OFFSET_512 0x40000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x48000 + /* * Internal Memories */ @@ -233,9 +240,6 @@ /* PIT Timer(PIT_PIIR) */ #define CONFIG_SYS_TIMER_COUNTER 0xf804803c -/* No PMECC Galois table in ROM */ -#define NO_GALOIS_TABLE_IN_ROM - #ifndef __ASSEMBLY__ unsigned int get_chip_id(void); unsigned int get_extension_chip_id(void); From af612ee4184d9fe9b17a9d81e65beeb8fceb8949 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 25 Feb 2022 10:13:56 +0200 Subject: [PATCH 02/11] configs: Convert AT91RESET_EXTRST to Kconfig Convert AT91RESET_EXTRST to Kconfig for easier integration. The symbol is not configurable from menuconfig, it will be automatically selected by SoCs that select it explicitly via the "select" directive. AT91RESET_EXTRST sets the Reset Controller's RSTC_CR.EXTRST bit which asserts the nrst_out pin that resets external devices. Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 145c4b276b..65589508d3 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -306,6 +306,9 @@ endchoice config ATMEL_SFR bool +config AT91RESET_EXTRST + bool + config SYS_SOC default "at91" From f206af80f8654dd6db57f021779e93e84ecb8fed Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 25 Feb 2022 10:13:57 +0200 Subject: [PATCH 03/11] ARM: at91: sama7g5: Reset external devices at software reset sama7g5 and other SoCs (sama5d3, sam9x60) define in the Reset Controller a RSTC_CR.EXTRST bit that asserts the nrst_out pin which resets external devices. This is particular useful for external devices that are configured in stateful modes which can not be undone without reconfiguring the device or without resetting the device. An example is an SPI NOR flash that is configured in octal mode. The do_reset u-boot cmd does not call any driver's remove method, but merely resets the CPU. As the code was, this left the flash in octal mode, being impossible for the first stage boot loaders to recover/identify the flash after a "software reset". RSTC_CR.EXTRST comes in handy here, as it can be set at "software reset" to assert low the nrst_out pin during a time defined by the RSTC_MR.ERSTL field and reset the external devices (including the SPI NOR flash in the example). nrst_out is always asserted at "user reset" and it resets the external devices correctly. Asserting nrst_out at "software reset" should behave in a similar way. The only difference that I could find between the two types of resets in regards to the nrst_out signal, is that at "user reset" timing diagram the "Processor and Peripherals Reset Line" rises after six MD_SLCK cycles after the nrst_out line rose, while at the "software reset" timing diagram the "Processor and Peripherals Reset Line" is active for 3 MD_SLCK cycles + 2 MCK cycles. In other words, in the "software reset" case the nrst_out signal can be active for a longer period of time than the "Processor and Peripherals Reset Line" active time, depending on the RSTC_MR.ERSTL value. Using the default value (zero) for RSTC_MR.ERSTL, worked just fine for the sama7g5 case. Tested QSPI0 and GMAC0/GMAC1 on sama7g5ek rev 4 after a software reset with RSTC_CR.EXTRST=1 and RSTC_MR.ERSTL=0. Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 65589508d3..488a43ad4f 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -50,6 +50,7 @@ config SAM9X60 config SAMA7G5 bool select CPU_V7A + select AT91RESET_EXTRST config SAMA5D2 bool From d05fc47bbc6e95f6cc16baa74d10fc40488d6798 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Mon, 7 Mar 2022 11:20:50 +0200 Subject: [PATCH 04/11] board: at91: sama5d2: set blue led on at boot time Set blue led on at boot time in order to highlight that u-boot is loaded. This is done for all sama5d2 based boards which contain an RGB led. Signed-off-by: Mihai Sain --- board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 9 +++++++++ board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 9 +++++++++ board/atmel/sama5d2_icp/sama5d2_icp.c | 9 +++++++++ board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c | 9 +++++++++ board/atmel/sama5d2_xplained/sama5d2_xplained.c | 9 +++++++++ 5 files changed, 45 insertions(+) diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 8c0cf3da54..b69f1c8cfa 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -22,6 +22,13 @@ extern void at91_pda_detect(void); DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 10, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 0); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 1); /* LED BLUE */ +} + #ifdef CONFIG_CMD_USB static void board_usb_hw_init(void) { @@ -71,6 +78,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + rgb_leds_init(); + #ifdef CONFIG_CMD_USB board_usb_hw_init(); #endif diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 32d51bba7d..67ada27072 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -22,6 +22,13 @@ extern void at91_pda_detect(void); DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 0); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 1); /* LED BLUE */ +} + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -64,6 +71,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + rgb_leds_init(); + return 0; } diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 3f33fcfc46..da697a7b0f 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -19,6 +19,13 @@ DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 0); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 1); /* LED BLUE */ +} + int board_late_init(void) { return 0; @@ -52,6 +59,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + rgb_leds_init(); + return 0; } diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 2a2439c53a..cca5bd1d8a 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -25,6 +25,13 @@ extern void at91_pda_detect(void); DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 6, 1); /* LED BLUE */ +} + #ifdef CONFIG_NAND_ATMEL static void board_nand_hw_init(void) { @@ -113,6 +120,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + rgb_leds_init(); + #ifdef CONFIG_NAND_ATMEL board_nand_hw_init(); #endif diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 8b5cd533d0..4bbb05c2fb 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -21,6 +21,13 @@ extern void at91_pda_detect(void); DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 6, 1); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 5, 1); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* LED BLUE */ +} + #ifdef CONFIG_CMD_USB static void board_usb_hw_init(void) { @@ -70,6 +77,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + rgb_leds_init(); + #ifdef CONFIG_CMD_USB board_usb_hw_init(); #endif From 29641527acde1501fcbbc1904fe55f69351ce55f Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 7 Mar 2022 16:29:41 +0200 Subject: [PATCH 05/11] ARM: dts: at91: rename sama7g5ek.dts to at91-sama7g5ek.dts In Linux this DT file is named at91-sama7g5ek.dts. Rename it accordingly. Signed-off-by: Eugen Hristev Reviewed-by: Tudor Ambarus --- arch/arm/dts/Makefile | 2 +- .../dts/{sama7g5ek-u-boot.dtsi => at91-sama7g5ek-u-boot.dtsi} | 3 ++- arch/arm/dts/{sama7g5ek.dts => at91-sama7g5ek.dts} | 2 +- configs/sama7g5ek_mmc1_defconfig | 2 +- configs/sama7g5ek_mmc_defconfig | 2 +- 5 files changed, 6 insertions(+), 5 deletions(-) rename arch/arm/dts/{sama7g5ek-u-boot.dtsi => at91-sama7g5ek-u-boot.dtsi} (89%) rename arch/arm/dts/{sama7g5ek.dts => at91-sama7g5ek.dts} (99%) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index beaaf15131..1c2de0a4d1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1046,7 +1046,7 @@ dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \ omap5-uevm.dtb dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ - sama7g5ek.dtb + at91-sama7g5ek.dtb dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ at91-sama5d2_ptc_ek.dtb diff --git a/arch/arm/dts/sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi similarity index 89% rename from arch/arm/dts/sama7g5ek-u-boot.dtsi rename to arch/arm/dts/at91-sama7g5ek-u-boot.dtsi index 5e1a0d53a5..652464f1e8 100644 --- a/arch/arm/dts/sama7g5ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * sama7g5ek-u-boot.dts - Device Tree file for SAMA7G5 SoC u-boot properties. + * at91-sama7g5ek-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot + * properties. * * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries * diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts similarity index 99% rename from arch/arm/dts/sama7g5ek.dts rename to arch/arm/dts/at91-sama7g5ek.dts index ac6f23f64e..38b3245751 100644 --- a/arch/arm/dts/sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * sama7g5ek.dts - Device Tree file for SAMA7G5 EK + * at91-sama7g5ek.dts - Device Tree file for SAMA7G5 EK * SAMA7G5 Evaluation Kit * * Copyright (c) 2020, Microchip Technology Inc. diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index a491268734..4ad8115d3a 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x60000000 CONFIG_SYS_MEMTEST_END=0x70000000 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="sama7g5ek" +CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g5ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xe1824200 CONFIG_DEBUG_UART_CLOCK=200000000 diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index 6891baac03..7bbe6565ef 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x60000000 CONFIG_SYS_MEMTEST_END=0x70000000 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="sama7g5ek" +CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g5ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xe1824200 CONFIG_DEBUG_UART_CLOCK=200000000 From 746b738224addbbe2d0b2e0faf8e526548192c4a Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 7 Mar 2022 16:29:42 +0200 Subject: [PATCH 06/11] ARM: dts: at91: sama7g5/sama7g5ek: align with Linux DT Align the DT for sama7g5 SoC and sama7g5 EK board with Linux devicetree in version 5.18. Some things remain still different, due to some things yet unimplemented in certain drivers. These include in PMC, pinctrl, and others. Signed-off-by: Eugen Hristev Reviewed-by: Tudor Ambarus --- arch/arm/dts/at91-sama7g5ek-u-boot.dtsi | 28 +- arch/arm/dts/at91-sama7g5ek.dts | 741 +++++++++++++++--- arch/arm/dts/sama7g5.dtsi | 960 ++++++++++++++++++++---- 3 files changed, 1447 insertions(+), 282 deletions(-) diff --git a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi index 652464f1e8..601386788f 100644 --- a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * at91-sama7g5ek-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot - * properties. + * at91-sama7g5ek-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot + * properties. * - * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries * - * Author: Eugen Hristev - * Author: Claudiu Beznea + * Author: Eugen Hristev + * Author: Claudiu Beznea * */ @@ -15,12 +15,8 @@ u-boot,dm-pre-reloc; }; - ahb { + soc { u-boot,dm-pre-reloc; - - apb { - u-boot,dm-pre-reloc; - }; }; }; @@ -32,18 +28,18 @@ u-boot,dm-pre-reloc; }; -&pioA { +&pinctrl { u-boot,dm-pre-reloc; - - pinctrl { - u-boot,dm-pre-reloc; - }; }; &pinctrl_flx3_default { u-boot,dm-pre-reloc; }; +&pioA { + u-boot,dm-pre-reloc; +}; + &pit64b0 { u-boot,dm-pre-reloc; }; @@ -60,7 +56,7 @@ u-boot,dm-pre-reloc; }; -&uart0 { +&uart3 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts index 38b3245751..5313c6d160 100644 --- a/arch/arm/dts/at91-sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -1,69 +1,150 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * at91-sama7g5ek.dts - Device Tree file for SAMA7G5 EK - * SAMA7G5 Evaluation Kit + * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries + * + * Author: Eugen Hristev + * Author: Claudiu Beznea * - * Copyright (c) 2020, Microchip Technology Inc. - * 2020, Eugen Hristev - * 2020, Claudiu Beznea */ /dts-v1/; -#include -#include "sama7g5.dtsi" #include "sama7g5-pinfunc.h" +#include "sama7g5.dtsi" +#include +#include #include / { - model = "Microchip SAMA7G5 Evaluation Kit"; - compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7"; - - aliases { - serial0 = &uart0; - i2c0 = &i2c1; - i2c1 = &i2c8; - }; + model = "Microchip SAMA7G5-EK"; + compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; chosen { + bootargs = "rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait"; stdout-path = "serial0:115200n8"; }; + aliases { + serial0 = &uart3; + serial1 = &uart4; + serial2 = &uart7; + serial3 = &uart0; + i2c0 = &i2c1; + i2c1 = &i2c8; + i2c2 = &i2c9; + }; + clocks { - slow_xtal: slow_xtal { + slow_xtal { clock-frequency = <32768>; }; - main_xtal: main_xtal { + main_xtal { clock-frequency = <24000000>; }; }; - ahb { + gpio_keys { + compatible = "gpio-keys"; - apb { - sdmmc0: sdio-host@e1204000 { - bus-width = <8>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_data_default - &pinctrl_sdmmc0_ck_rstn_ds_cd_default>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + bp1 { + label = "PB_USER"; + gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; /* Conflict with pwm. */ + + red_led { + label = "red"; + gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; + }; + + green_led { + label = "green"; + gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>; + }; + + blue_led { + label = "blue"; + gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* 512 M */ + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x20000000>; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sama7g5ek audio"; + #address-cells = <1>; + #size-cells = <0>; + simple-audio-card,dai-link@0 { + reg = <0>; + cpu { + sound-dai = <&spdiftx>; }; - - sdmmc1: sdio-host@e1208000 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default - &pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>; - status = "okay"; + codec { + sound-dai = <&spdif_out>; }; - - uart0: serial@e1824200 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx3_default>; - status = "okay"; + }; + simple-audio-card,dai-link@1 { + reg = <1>; + cpu { + sound-dai = <&spdifrx>; + }; + codec { + sound-dai = <&spdif_in>; }; }; }; + + spdif_in: spdif-in { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&adc { + vddana-supply = <&vddout25>; + vref-supply = <&vddout25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; }; &qspi0 { @@ -81,18 +162,233 @@ spi-rx-bus-width = <8>; m25p,fast-read; + at91bootstrap@0 { + label = "ospi: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "ospi: bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "ospi: bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "ospi: bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "ospi: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "ospi: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "ospi: rootfs"; + reg = <0x800000 0x7800000>; + }; + + }; +}; + +&dma0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "disabled"; + + uart0: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + status = "disabled"; }; }; &flx1 { atmel,flexcom-mode = ; status = "okay"; + + i2c1: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-voltage = <1150000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-voltage = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-voltage = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + + regulator-state-standby { + regulator-suspend-voltage = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; }; -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx1_default>; +&flx3 { + atmel,flexcom-mode = ; status = "okay"; + + uart3: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + uart4: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + status = "okay"; + }; +}; + +&flx7 { + atmel,flexcom-mode = ; + status = "okay"; + + uart7: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx7_default>; + status = "okay"; + }; }; &flx8 { @@ -121,18 +417,46 @@ }; }; +&flx9 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c9: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + }; +}; + +&flx11 { + atmel,flexcom-mode = ; + status = "okay"; + + spi11: spi@400 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; + status = "okay"; + }; +}; + &gmac0 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_mdio_default - &pinctrl_gmac0_txc_default>; + &pinctrl_gmac0_txck_default + &pinctrl_gmac0_phy_irq>; phy-mode = "rgmii-id"; status = "okay"; ethernet-phy@7 { reg = <0x7>; + interrupt-parent = <&pioA>; + interrupts = ; }; }; @@ -140,19 +464,43 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_mdio_default>; + pinctrl-0 = <&pinctrl_gmac1_default + &pinctrl_gmac1_mdio_default + &pinctrl_gmac1_phy_irq>; phy-mode = "rmii"; status = "okay"; ethernet-phy@0 { reg = <0x0>; + interrupt-parent = <&pioA>; + interrupts = ; }; }; -&pinctrl { - pinctrl_flx1_default: flx1_default { - pinmux = , - ; +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s0_default>; +}; + +&pioA { + + pinctrl_can0_default: can0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_flx0_default: flx0_default { + pinmux = , + , + , + ; bias-disable; }; @@ -162,67 +510,16 @@ bias-pull-up; }; - pinctrl_i2c8_default: i2c8_default { - pinmux = , - ; + pinctrl_flx4_default: flx4_default { + pinmux = , + ; bias-disable; }; - pinctrl_qspi: qspi { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - ; + pinctrl_flx7_default: flx7_default { + pinmux = , + ; bias-disable; - slew-rate = <0>; - atmel,drive-strength = ; - }; - - pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default { - pinmux = , - , - , - , - , - , - , - , - ; - bias-pull-up; - }; - - pinctrl_sdmmc0_ck_rstn_ds_cd_default: sdmmc0_ck_rstn_ds_cd_default { - pinmux = , - , - , - ; - bias-pull-up; - }; - - pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default { - pinmux = , - , - , - , - ; - bias-pull-up; - }; - - pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default { - pinmux = , - , - , - ; - bias-pull-up; }; pinctrl_gmac0_default: gmac0_default { @@ -248,12 +545,17 @@ bias-disable; }; - pinctrl_gmac0_txc_default: gmac0_txc_default { + pinctrl_gmac0_txck_default: gmac0_txck_default { pinmux = ; slew-rate = <0>; bias-pull-up; }; + pinctrl_gmac0_phy_irq: gmac0_phy_irq { + pinmux = ; + bias-disable; + }; + pinctrl_gmac1_default: gmac1_default { pinmux = , , @@ -272,4 +574,231 @@ ; bias-disable; }; + + pinctrl_gmac1_phy_irq: gmac1_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c8_default: i2c8_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c9_default: i2c9_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2s0_default: i2s0_default { + pinmux = , + , + , + , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_mikrobus1_an_default: mikrobus1_an_default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_an_default: mikrobus2_an_default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi: mikrobus1_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_qspi: qspi { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + slew-rate = <0>; + atmel,drive-strength = ; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = <0>; + bias-pull-up; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <0>; + bias-pull-up; + }; + + pinctrl_sdmmc2_default: sdmmc2_default { + pinmux = , + , + , + , + , + ; + slew-rate = <0>; + bias-pull-up; + }; + + pinctrl_spdifrx_default: spdifrx_default { + pinmux = ; + bias-disable; + }; + + pinctrl_spdiftx_default: spdiftx_default { + pinmux = ; + bias-disable; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>; + status = "disabled"; /* Conflict with leds. */ +}; + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width = <8>; + non-removable; + no-1-8-v; + sdhci-caps-mask = <0x0 0x00200000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + no-1-8-v; + sdhci-caps-mask = <0x0 0x00200000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + no-1-8-v; + sdhci-caps-mask = <0x0 0x00200000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc2_default>; +}; + +&shdwc { + atmel,shdwc-debouncer = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&spdifrx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdifrx_default>; + status = "okay"; +}; + +&spdiftx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdiftx_default>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&trng { + status = "okay"; +}; + +&vddout25 { + vin-supply = <&vdd_3v3>; + status = "okay"; }; diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index 2505a2f83d..b7c261ebe9 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC. + * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC * - * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries + * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries * - * Author: Eugen Hristev - * Author: Claudiu Beznea + * Author: Eugen Hristev + * Author: Claudiu Beznea * */ @@ -14,12 +14,63 @@ #include #include #include +#include / { model = "Microchip SAMA7G5 family SoC"; compatible = "microchip,sama7g5"; + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>; + clock-names = "cpu", "master", "xtal"; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-90000000 { + opp-hz = /bits/ 64 <90000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + opp-suspend; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1150000 1125000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-1000000002 { + opp-hz = /bits/ 64 <1000000002>; + opp-microvolt = <1250000 1225000 1300000>; + clock-latency-ns = <320000>; + }; + }; + clocks { slow_rc_osc: slow_rc_osc { compatible = "fixed-clock"; @@ -42,205 +93,794 @@ compatible = "fixed-clock"; #clock-cells = <0>; }; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>; - clock-names = "cpu", "master", "xtal"; + usb_clk: usb_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; }; }; - ahb { + vddout25: fixed-regulator-vddout25 { + compatible = "regulator-fixed"; + + regulator-name = "VDDOUT25"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + status = "disabled"; + }; + + ns_sram: sram@100000 { + compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100000 0x20000>; + ranges; + }; + + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + ranges; - apb { - compatible = "simple-bus"; + nfc_sram: sram@600000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x00600000 0x2400>; #address-cells = <1>; #size-cells = <1>; + ranges = <0 0x00600000 0x2400>; + }; - pioA: pinctrl@e0014000 { - compatible = "microchip,sama7g5-gpio"; - reg = <0xe0014000 0x800>; + nfc_io: nfc-io@10000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0x10000000 0x8000000>; + }; + + ebi: ebi@40000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x40000000 0x20000000>; + ranges = <0x0 0x0 0x40000000 0x8000000 + 0x1 0x0 0x48000000 0x8000000 + 0x2 0x0 0x50000000 0x8000000 + 0x3 0x0 0x58000000 0x8000000>; + clocks = <&pmc PMC_TYPE_CORE 13>; /* PMC_MCK1 */ + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + + securam: securam@e0000000 { + compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000000 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe0000000 0x4000>; + no-memory-wc; + }; + + secumod: secumod@e0004000 { + compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + + sfrbu: sfr@e0008000 { + compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; + reg = <0xe0008000 0x20>; + }; + + pinctrl: pinctrl@e0014000 { + compatible = "microchip,sama7g5-gpio"; + reg = <0xe0014000 0x800>; + interrupts = , + , + , + , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + + pioA: pinctrl_default { + interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "okay"; - - pinctrl: pinctrl_default { - compatible = "microchip,sama7g5-pinctrl"; - }; + compatible = "microchip,sama7g5-pinctrl"; }; + }; - pmc: pmc@e0018000 { - compatible = "microchip,sama7g5-pmc"; - reg = <0xe0018000 0x200>; - #clock-cells = <2>; - clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>; - clock-names = "td_slck", "md_slck", "main_xtal", "main_rc"; - status = "okay"; + pmc: pmc@e0018000 { + compatible = "microchip,sama7g5-pmc", "syscon"; + reg = <0xe0018000 0x200>; + interrupts = ; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>, <&main_rc>; + clock-names = "td_slck", "md_slck", "main_xtal", "main_rc"; + }; + + shdwc: shdwc@e001d010 { + compatible = "microchip,sama7g5-shdwc", "syscon"; + reg = <0xe001d010 0x10>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtt@e001d020 { + compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d020 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + + clk32k: clock-controller@e001d050 { + compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; + reg = <0xe001d050 0x4>; + clocks = <&slow_rc_osc>, <&slow_xtal>; + #clock-cells = <1>; + }; + + gpbr: gpbr@e001d060 { + compatible = "microchip,sama7g5-gpbr", "syscon"; + reg = <0xe001d060 0x48>; + }; + + rtc: rtc@e001d0a8 { + compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; + reg = <0xe001d0a8 0x30>; + interrupts = ; + clocks = <&clk32k 1>; + }; + + ps_wdt: watchdog@e001d180 { + compatible = "microchip,sama7g5-wdt"; + reg = <0xe001d180 0x24>; + interrupts = ; + clocks = <&clk32k 0>; + }; + + chipid@e0020000 { + compatible = "microchip,sama7g5-chipid"; + reg = <0xe0020000 0x8>; + }; + + tcb1: timer@e0800000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0800000 0x100>; + interrupts = , , ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + hsmc: hsmc@e0808000 { + compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; + reg = <0xe0808000 0x1000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@e0808070 { + compatible = "atmel,sama5d2-pmecc"; + reg = <0xe0808070 0x490>, + <0xe0808500 0x200>; }; + }; - clk32: sckc@e001d050 { - compatible = "microchip,sam9x60-sckc"; - reg = <0xe001d050 0x4>; - clocks = <&slow_rc_osc>, <&slow_xtal>; - #clock-cells = <1>; - }; + qspi0: spi@e080c000 { + compatible = "microchip,sama7g5-ospi"; + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, + <&dma0 AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 78>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - qspi0: spi@e080c000 { - compatible = "microchip,sama7g5-ospi"; - reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; - reg-names = "qspi_base", "qspi_mmap"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; - clock-names = "pclk", "gclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 78>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + qspi1: spi@e0810000 { + compatible = "microchip,sama7g5-qspi"; + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, + <&dma0 AT91_XDMAC_DT_PERID(42)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 78>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - qspi1: spi@e0810000 { - compatible = "microchip,sama7g5-qspi"; - reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; - reg-names = "qspi_base", "qspi_mmap"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; - clock-names = "pclk", "gclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 78>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + can0: can@e0828000 { + compatible = "bosch,m_can"; + reg = <0xe0828000 0x100>, <0x100000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 61>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; - sdmmc0: sdio-host@e1204000 { - compatible = "microchip,sama7g5-sdhci"; - reg = <0xe1204000 0x300>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; - clock-names = "hclock", "multclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 80>; - assigned-clock-rates = <200000000>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ - status = "disabled"; - }; + can1: can@e082c000 { + compatible = "bosch,m_can"; + reg = <0xe082c000 0x100>, <0x100000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 62>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; - sdmmc1: sdio-host@e1208000 { - compatible = "microchip,sama7g5-sdhci"; - reg = <0xe1208000 0x300>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; - clock-names = "hclock", "multclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 81>; - assigned-clock-rates = <200000000>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ - status = "disabled"; - }; + can2: can@e0830000 { + compatible = "bosch,m_can"; + reg = <0xe0830000 0x100>, <0x100000 0x10000>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 63>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; + status = "disabled"; + }; - pit64b0: timer@e1800000 { - compatible = "microchip,sama7g5-pit64b"; - reg = <0xe1800000 0x4000>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; - clock-names = "pclk", "gclk"; - status = "okay"; - }; + can3: can@e0834000 { + compatible = "bosch,m_can"; + reg = <0xe0834000 0x100>, <0x110000 0x4400>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 64>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; - flx1: flexcom@e181c000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe181c000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe181c000 0x800>; - status = "disabled"; + can4: can@e0838000 { + compatible = "bosch,m_can"; + reg = <0xe0838000 0x100>, <0x110000 0x8800>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 65>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; + status = "disabled"; + }; - i2c1: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - }; - }; + can5: can@e083c000 { + compatible = "bosch,m_can"; + reg = <0xe083c000 0x100>, <0x110000 0xcc00>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 66>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; + status = "disabled"; + }; - uart0: serial@e1824200 { + adc: adc@e1000000 { + compatible = "microchip,sama7g5-adc"; + reg = <0xe1000000 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + clock-names = "adc_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; + dma-names = "rx"; + atmel,min-sample-rate-hz = <200000>; + atmel,max-sample-rate-hz = <20000000>; + atmel,startup-time-ms = <4>; + status = "disabled"; + }; + + sdmmc0: mmc@e1204000 { + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe1204000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; + clock-names = "hclock", "multclk"; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ + assigned-clocks = <&pmc PMC_TYPE_GCK 80>; + assigned-clock-rates = <200000000>; + microchip,sdcal-inverted; + status = "disabled"; + }; + + sdmmc1: mmc@e1208000 { + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe1208000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; + clock-names = "hclock", "multclk"; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ + assigned-clocks = <&pmc PMC_TYPE_GCK 81>; + assigned-clock-rates = <200000000>; + microchip,sdcal-inverted; + status = "disabled"; + }; + + sdmmc2: mmc@e120c000 { + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe120c000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; + clock-names = "hclock", "multclk"; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ + assigned-clocks = <&pmc PMC_TYPE_GCK 82>; + assigned-clock-rates = <200000000>; + microchip,sdcal-inverted; + status = "disabled"; + }; + + pwm: pwm@e1604000 { + compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; + reg = <0xe1604000 0x4000>; + interrupts = ; + #pwm-cells = <3>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; + status = "disabled"; + }; + + spdifrx: spdifrx@e1614000 { + #sound-dai-cells = <0>; + compatible = "microchip,sama7g5-spdifrx"; + reg = <0xe1614000 0x4000>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + spdiftx: spdiftx@e1618000 { + #sound-dai-cells = <0>; + compatible = "microchip,sama7g5-spdiftx"; + reg = <0xe1618000 0x4000>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; + clock-names = "pclk", "gclk"; + }; + + i2s0: i2s@e161c000 { + compatible = "microchip,sama7g5-i2smcc"; + #sound-dai-cells = <0>; + reg = <0xe161c000 0x4000>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + i2s1: i2s@e1620000 { + compatible = "microchip,sama7g5-i2smcc"; + #sound-dai-cells = <0>; + reg = <0xe1620000 0x4000>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + eic: interrupt-controller@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0xec>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + status = "disabled"; + }; + + pit64b0: timer@e1800000 { + compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1800000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; + clock-names = "pclk", "gclk"; + }; + + pit64b1: timer@e1804000 { + compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1804000 0x4000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; + clock-names = "pclk", "gclk"; + }; + + aes: crypto@e1810000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe1810000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "aes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + }; + + sha: crypto@e1814000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe1814000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; + clock-names = "sha_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + }; + + flx0: flexcom@e1818000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe1818000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe1818000 0x800>; + status = "disabled"; + + uart0: serial@200 { compatible = "atmel,at91sam9260-usart"; - reg = <0xe1824200 0x200>; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, + <&dma1 AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + }; + + flx1: flexcom@e181c000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe181c000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe181c000 0x800>; + status = "disabled"; + + i2c1: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + flx3: flexcom@e1824000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe1824000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe1824000 0x800>; + status = "disabled"; + + uart3: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, + <&dma1 AT91_XDMAC_DT_PERID(11)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; status = "disabled"; }; + }; - gmac0: ethernet@e2800000 { - compatible = "cdns,sama7g5-gem"; - reg = <0xe2800000 0x4000>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>; - clock-names = "hclk", "pclk", "tx_clk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 51>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */ - assigned-clock-rates = <125000000>; + trng: rng@e2010000 { + compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; + reg = <0xe2010000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; + status = "disabled"; + }; + + tdes: crypto@e2014000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xe2014000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; + clock-names = "tdes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, + <&dma0 AT91_XDMAC_DT_PERID(53)>; + dma-names = "tx", "rx"; + }; + + flx4: flexcom@e2018000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2018000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2018000 0x800>; + status = "disabled"; + + uart4: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, + <&dma1 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; status = "disabled"; }; + }; - gmac1: ethernet@e2804000 { - compatible = "cdns,sama7g5-emac"; - reg = <0xe2804000 0x1000>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; - clock-names = "pclk", "hclk"; + flx7: flexcom@e2024000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2024000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2024000 0x800>; + status = "disabled"; + + uart7: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; status = "disabled"; }; + }; - dma0: dma-controller@e2808000 { - compatible = "microchip,sama7g5-dma"; - reg = <0xe2808000 0x1000>; - interrupts = ; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "dma_clk"; - status = "disabled"; - }; + gmac0: ethernet@e2800000 { + compatible = "cdns,sama7g5-gem"; + reg = <0xe2800000 0x1000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 51>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */ + assigned-clock-rates = <125000000>; + status = "disabled"; + }; - flx8: flexcom@e2818000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xe2818000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; + gmac1: ethernet@e2804000 { + compatible = "cdns,sama7g5-emac"; + reg = <0xe2804000 0x1000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + dma0: dma-controller@e2808000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe2808000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + dma1: dma-controller@e280c000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe280c000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + /* Place dma2 here despite it's address */ + dma2: dma-controller@e1200000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe1200000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names = "dma_clk"; + dma-requests = <0>; + status = "disabled"; + }; + + tcb0: timer@e2814000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe2814000 0x100>; + interrupts = , , ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + flx8: flexcom@e2818000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2818000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2818000 0x800>; + status = "disabled"; + + i2c8: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe2818000 0x800>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, + <&dma0 AT91_XDMAC_DT_PERID(22)>; + dma-names = "rx", "tx"; status = "disabled"; - - i2c8: i2c@600 { - compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; - atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, - <&dma0 AT91_XDMAC_DT_PERID(22)>; - dma-names = "rx", "tx"; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; }; + }; - gic: interrupt-controller@e8c11000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - interrupt-parent; - reg = <0xe8c11000 0x1000>, - <0xe8c12000 0x2000>; + flx9: flexcom@e281c000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe281c000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe281c000 0x800>; + status = "disabled"; + + i2c9: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, + <&dma0 AT91_XDMAC_DT_PERID(24)>; + dma-names = "rx", "tx"; + status = "disabled"; }; }; + + flx11: flexcom@e2824000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2824000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2824000 0x800>; + status = "disabled"; + + spi11: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, + <&dma0 AT91_XDMAC_DT_PERID(28)>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupt-parent; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>; + }; }; }; From 70fb1ae9dd30b1dc6cf0c6ba585f822ef58106e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Thu, 31 Mar 2022 10:55:06 +0200 Subject: [PATCH 07/11] timer: atmel_tcb_timer: add atmel_tcb driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea Signed-off-by: Clément Léger --- MAINTAINERS | 1 + arch/arm/mach-at91/armv7/Makefile | 2 + drivers/timer/Kconfig | 8 ++ drivers/timer/Makefile | 1 + drivers/timer/atmel_tcb_timer.c | 161 ++++++++++++++++++++++++++++++ 5 files changed, 173 insertions(+) create mode 100644 drivers/timer/atmel_tcb_timer.c diff --git a/MAINTAINERS b/MAINTAINERS index 74d5263fb1..b22aaa30b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -352,6 +352,7 @@ F: arch/arm/mach-at91/ F: board/atmel/ F: drivers/cpu/at91_cpu.c F: drivers/misc/microchip_flexcom.c +F: drivers/timer/atmel_tcb_timer.c F: include/dt-bindings/mfd/atmel-flexcom.h F: drivers/timer/mchp-pit64b-timer.c diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 246050b67b..f395b55c3d 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -14,9 +14,11 @@ obj-y += cpu.o ifndef CONFIG_$(SPL_TPL_)SYSRESET obj-y += reset.o endif +ifneq ($(CONFIG_ATMEL_TCB_TIMER),y) ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) ifneq ($(CONFIG_MCHP_PIT64B_TIMER),y) # old non-DM timer driver obj-y += timer.o endif endif +endif diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 8913142654..8fad59b81a 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -96,6 +96,14 @@ config ATMEL_PIT_TIMER it is designed to offer maximum accuracy and efficient management, even for systems with long response time. +config ATMEL_TCB_TIMER + bool "Atmel timer counter support" + depends on TIMER + depends on ARCH_AT91 + help + Select this to enable the use of the timer counter as a monotonic + counter. + config CADENCE_TTC_TIMER bool "Cadence TTC (Triple Timer Counter)" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index e2bd530eb0..58da6c1e84 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o +obj-$(CONFIG_ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o diff --git a/drivers/timer/atmel_tcb_timer.c b/drivers/timer/atmel_tcb_timer.c new file mode 100644 index 0000000000..8c17987c7d --- /dev/null +++ b/drivers/timer/atmel_tcb_timer.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Microchip Corporation + * + * Author: Clément Léger + */ + +#include +#include +#include +#include +#include +#include + +#define TCB_CHAN(chan) ((chan) * 0x40) + +#define TCB_CCR(chan) (0x0 + TCB_CHAN(chan)) +#define TCB_CCR_CLKEN (1 << 0) + +#define TCB_CMR(chan) (0x4 + TCB_CHAN(chan)) +#define TCB_CMR_WAVE (1 << 15) +#define TCB_CMR_TIMER_CLOCK2 1 +#define TCB_CMR_XC1 6 +#define TCB_CMR_ACPA_SET (1 << 16) +#define TCB_CMR_ACPC_CLEAR (2 << 18) + +#define TCB_CV(chan) (0x10 + TCB_CHAN(chan)) + +#define TCB_RA(chan) (0x14 + TCB_CHAN(chan)) +#define TCB_RC(chan) (0x1c + TCB_CHAN(chan)) + +#define TCB_IDR(chan) (0x28 + TCB_CHAN(chan)) + +#define TCB_BCR 0xc0 +#define TCB_BCR_SYNC (1 << 0) + +#define TCB_BMR 0xc4 +#define TCB_BMR_TC1XC1S_TIOA0 (2 << 2) + +#define TCB_WPMR 0xe4 +#define TCB_WPMR_WAKEY 0x54494d + +#define TCB_CLK_DIVISOR 8 +struct atmel_tcb_plat { + void __iomem *base; +}; + +static u64 atmel_tcb_get_count(struct udevice *dev) +{ + struct atmel_tcb_plat *plat = dev_get_plat(dev); + u64 cv0 = 0; + u64 cv1 = 0; + + do { + cv1 = readl(plat->base + TCB_CV(1)); + cv0 = readl(plat->base + TCB_CV(0)); + } while (readl(plat->base + TCB_CV(1)) != cv1); + + cv0 |= cv1 << 32; + + return cv0; +} + +static void atmel_tcb_configure(void __iomem *base) +{ + /* Disable write protection */ + writel(TCB_WPMR_WAKEY, base + TCB_WPMR); + + /* Disable all irqs for both channel 0 & 1 */ + writel(0xff, base + TCB_IDR(0)); + writel(0xff, base + TCB_IDR(1)); + + /* + * In order to avoid wrapping, use a 64 bit counter by chaining + * two channels. + * Channel 0 is configured to generate a clock on TIOA0 which is cleared + * when reaching 0x80000000 and set when reaching 0. + */ + writel(TCB_CMR_TIMER_CLOCK2 | TCB_CMR_WAVE | TCB_CMR_ACPA_SET + | TCB_CMR_ACPC_CLEAR, base + TCB_CMR(0)); + writel(0x80000000, base + TCB_RC(0)); + writel(0x1, base + TCB_RA(0)); + writel(TCB_CCR_CLKEN, base + TCB_CCR(0)); + + /* Channel 1 is configured to use TIOA0 as input */ + writel(TCB_CMR_XC1 | TCB_CMR_WAVE, base + TCB_CMR(1)); + writel(TCB_CCR_CLKEN, base + TCB_CCR(1)); + + /* Set XC1 input to be TIOA0 (ie output of Channel 0) */ + writel(TCB_BMR_TC1XC1S_TIOA0, base + TCB_BMR); + + /* Sync & start all timers */ + writel(TCB_BCR_SYNC, base + TCB_BCR); +} + +static int atmel_tcb_probe(struct udevice *dev) +{ + struct atmel_tcb_plat *plat = dev_get_plat(dev); + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk clk; + ulong clk_rate; + int ret; + + if (!device_is_compatible(dev->parent, "atmel,sama5d2-tcb")) + return -EINVAL; + + /* Currently, we only support channel 0 and 1 to be chained */ + if (dev_read_addr_index(dev, 0) != 0 && + dev_read_addr_index(dev, 1) != 1) { + printf("Error: only chained timers 0 and 1 are supported\n"); + return -EINVAL; + } + + ret = clk_get_by_name(dev->parent, "t0_clk", &clk); + if (ret) + return -EINVAL; + + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) { + clk_disable(&clk); + return -EINVAL; + } + + uc_priv->clock_rate = clk_rate / TCB_CLK_DIVISOR; + + atmel_tcb_configure(plat->base); + + return 0; +} + +static int atmel_tcb_of_to_plat(struct udevice *dev) +{ + struct atmel_tcb_plat *plat = dev_get_plat(dev); + + plat->base = dev_read_addr_ptr(dev->parent); + + return 0; +} + +static const struct timer_ops atmel_tcb_ops = { + .get_count = atmel_tcb_get_count, +}; + +static const struct udevice_id atmel_tcb_ids[] = { + { .compatible = "atmel,tcb-timer" }, + { } +}; + +U_BOOT_DRIVER(atmel_tcb) = { + .name = "atmel_tcb", + .id = UCLASS_TIMER, + .of_match = atmel_tcb_ids, + .of_to_plat = atmel_tcb_of_to_plat, + .plat_auto = sizeof(struct atmel_tcb_plat), + .probe = atmel_tcb_probe, + .ops = &atmel_tcb_ops, +}; From d29e55a6c23dac4b8dc51e1fbd19037c4deaf35b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Thu, 31 Mar 2022 10:55:07 +0200 Subject: [PATCH 08/11] ARM: dts: at91: sama5d2: add AIC node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When using interrupts property, a global interrupt controller needs to be added to avoid warnings when compiling device-tree: arch/arm/dts/at91-sama5d2_xplained.dtb: Warning (interrupts_property): /ahb/apb/timer@f800c000: Missing interrupt-parent Add AIC node as the sama5d2 global interrupt controller. Signed-off-by: Clément Léger --- arch/arm/dts/sama5d2.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 038cd73c03..7de58e4a1f 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -3,6 +3,7 @@ / { model = "Atmel SAMA5D2 family SoC"; compatible = "atmel,sama5d2"; + interrupt-parent = <&aic>; aliases { spi0 = &spi0; @@ -762,6 +763,14 @@ status = "disabled"; }; + aic: interrupt-controller@fc020000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d2-aic"; + interrupt-controller; + reg = <0xfc020000 0x200>; + atmel,external-irqs = <49>; + }; + i2c1: i2c@fc028000 { compatible = "atmel,sama5d2-i2c"; reg = <0xfc028000 0x100>; From 757647313dd69324c5a01125b5ce9664058fee50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Thu, 31 Mar 2022 10:55:08 +0200 Subject: [PATCH 09/11] ARM: dts: at91: sama5d2: add TCB node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the device-tree node to describe the TCB timer. Signed-off-by: Clément Léger --- arch/arm/dts/sama5d2.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 7de58e4a1f..058009adca 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include / { model = "Atmel SAMA5D2 family SoC"; @@ -639,6 +640,21 @@ status = "disabled"; }; + tcb0: timer@f800c000 { + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; + reg = <0xf800c000 0x100>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&tcb0_gclk>, <&clk32k>; + clock-names = "t0_clk", "gclk", "slow_clk"; + #address-cells = <1>; + #size-cells = <0>; + + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + }; + uart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x100>; From 3d3fdaf0758f1fe240774a7394d6cf04573ffd5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Thu, 31 Mar 2022 10:55:09 +0200 Subject: [PATCH 10/11] ARM: dts: at91: sama5d2: add u-boot, dm-pre-reloc property for TCB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to use the TCB early in boot and in the SPL, add u-boot,dm-pre-reloc property for the TCB and the clock that is used by the driver (tcb0_clk). Signed-off-by: Clément Léger --- arch/arm/dts/sama5d2.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 058009adca..d92bdd5588 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -363,6 +363,7 @@ #clock-cells = <0>; reg = <35>; atmel,clk-output-range = <0 83000000>; + u-boot,dm-pre-reloc; }; tcb1_clk: tcb1_clk@36 { @@ -648,10 +649,12 @@ clock-names = "t0_clk", "gclk", "slow_clk"; #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc; timer0: timer@0 { compatible = "atmel,tcb-timer"; reg = <0>, <1>; + u-boot,dm-pre-reloc; }; }; From ef9d9b2501ad9e0601bd292c4a6c8a7ba8f3a909 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Thu, 31 Mar 2022 10:55:10 +0200 Subject: [PATCH 11/11] configs: sama5d2: enable option CONFIG_ATMEL_TCB_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CONFIG_ATMEL_TCB_TIMER and disable CONFIG_ATMEL_PIT_TIMER. This will allow using the TCB timer instead of the PIT one when running under OP-TEE. Reviewed-by: Claudiu Beznea Signed-off-by: Clément Léger --- configs/sama5d2_icp_mmc_defconfig | 2 +- configs/sama5d2_ptc_ek_mmc_defconfig | 2 +- configs/sama5d2_ptc_ek_nandflash_defconfig | 2 +- configs/sama5d2_xplained_emmc_defconfig | 2 +- configs/sama5d2_xplained_mmc_defconfig | 2 +- configs/sama5d2_xplained_qspiflash_defconfig | 2 +- configs/sama5d2_xplained_spiflash_defconfig | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 5b530f0da6..ef92009078 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -82,6 +82,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y -CONFIG_ATMEL_PIT_TIMER=y +CONFIG_ATMEL_TCB_TIMER=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER_HII is not set diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index 609e202c34..1c5d750fe5 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -71,7 +71,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_TIMER=y -CONFIG_ATMEL_PIT_TIMER=y +CONFIG_ATMEL_TCB_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index 132f31a3d4..690361a0f1 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -71,7 +71,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_TIMER=y -CONFIG_ATMEL_PIT_TIMER=y +CONFIG_ATMEL_TCB_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index caacbabb7b..a47b3346be 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -91,7 +91,7 @@ CONFIG_DM_SPI=y CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y -CONFIG_ATMEL_PIT_TIMER=y +CONFIG_ATMEL_TCB_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index de9fe9d13b..4b656ca75b 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -93,7 +93,7 @@ CONFIG_DM_SPI=y CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y -CONFIG_ATMEL_PIT_TIMER=y +CONFIG_ATMEL_TCB_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 24b509d062..4c56efcc50 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -92,7 +92,7 @@ CONFIG_DM_SPI=y CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y -CONFIG_ATMEL_PIT_TIMER=y +CONFIG_ATMEL_TCB_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index e4a2e45965..bd3a70c954 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -96,7 +96,7 @@ CONFIG_DM_SPI=y CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y -CONFIG_ATMEL_PIT_TIMER=y +CONFIG_ATMEL_TCB_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y