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ARM: DRA7xx: Correct SRAM END address

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NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Sricharan R 2013-05-30 03:19:35 +00:00 committed by Tom Rini
parent f9b814a8e9
commit 81ede187c3
1 changed files with 6 additions and 5 deletions
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11
arch/arm/include/asm/arch-omap5/omap.h
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@ -169,13 +169,14 @@ struct s32ktimer {
#define EFUSE_4 0x45145100 #define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
/* #ifdef CONFIG_DRA7XX
* Non-secure SRAM Addresses #define NON_SECURE_SRAM_START 0x40300000
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
* at 0x40304000(EMU base) so that our code works for both EMU and GP #else
*/
#define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
#endif
/* base address for indirect vectors (internal boot mode) */ /* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000 #define SRAM_ROM_VECT_BASE 0x4031F000