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ARM: uniphier: add more init code for PXs3

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Add the boot device table and reset deassertion for eMMC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2017-05-15 14:26:33 +09:00
parent edee114a8b
commit 81afa9c9a3
9 changed files with 76 additions and 1 deletions
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1
arch/arm/mach-uniphier/board_init.c
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@ -175,6 +175,7 @@ static const struct uniphier_initdata uniphier_initdata[] = {
.nand_2cs = false,
.sbc_init = uniphier_pxs2_sbc_init,
.pll_init = uniphier_pxs3_pll_init,
.clk_init = uniphier_pxs3_clk_init,
},
#endif
};

1
arch/arm/mach-uniphier/boot-device/Makefile
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@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-device-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-device-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-device-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-device-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += boot-device-pxs3.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o

41
arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c Normal file
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@ -0,0 +1,41 @@
/*
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "../sg-regs.h"
#include "boot-device.h"
const struct uniphier_boot_device uniphier_pxs3_boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"},
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5, BBM Last Page)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5, BBM Last Page)"},
};
const unsigned uniphier_pxs3_boot_device_count =
ARRAY_SIZE(uniphier_pxs3_boot_device_table);
int uniphier_pxs3_boot_device_is_usb(u32 pinmon)
{
return !!(readl(SG_PINMON2) & BIT(31));
}

10
arch/arm/mach-uniphier/boot-device/boot-device.c
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@ -115,6 +115,16 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
.have_internal_stm = 1,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
{
.soc_id = UNIPHIER_PXS3_ID,
.boot_device_sel_shift = 1,
.boot_device_table = uniphier_pxs3_boot_device_table,
.boot_device_count = &uniphier_pxs3_boot_device_count,
.boot_device_is_usb = uniphier_pxs3_boot_device_is_usb,
.have_internal_stm = 0,
},
#endif
};
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_boot_device_info,
uniphier_boot_device_info)

3
arch/arm/mach-uniphier/boot-device/boot-device.h
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@ -18,16 +18,19 @@ extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[];
extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[];
extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[];
extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[];
extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[];
extern const unsigned int uniphier_sld3_boot_device_count;
extern const unsigned int uniphier_ld4_boot_device_count;
extern const unsigned int uniphier_pro5_boot_device_count;
extern const unsigned int uniphier_pxs2_boot_device_count;
extern const unsigned int uniphier_ld11_boot_device_count;
extern const unsigned int uniphier_pxs3_boot_device_count;
int uniphier_pxs2_boot_device_is_usb(u32 pinmon);
int uniphier_ld11_boot_device_is_usb(u32 pinmon);
int uniphier_ld20_boot_device_is_usb(u32 pinmon);
int uniphier_pxs3_boot_device_is_usb(u32 pinmon);
unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode);
unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode);

2
arch/arm/mach-uniphier/clk/Makefile
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@ -25,7 +25,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-pxs3.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o
endif

17
arch/arm/mach-uniphier/clk/clk-pxs3.c Normal file
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@ -0,0 +1,17 @@
/*
* Copyright (C) 2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#define SDCTRL_EMMC_HW_RESET 0x59810280
void uniphier_pxs3_clk_init(void)
{
/* TODO: use "mmc-pwrseq-emmc" */
writel(1, SDCTRL_EMMC_HW_RESET);
}

1
arch/arm/mach-uniphier/init.h
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@ -119,6 +119,7 @@ void uniphier_pro5_clk_init(void);
void uniphier_pxs2_clk_init(void);
void uniphier_ld11_clk_init(void);
void uniphier_ld20_clk_init(void);
void uniphier_pxs3_clk_init(void);
unsigned int uniphier_boot_device_raw(void);
int uniphier_have_internal_stm(void);

1
arch/arm/mach-uniphier/sg-regs.h
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@ -70,6 +70,7 @@
/* Pin Monitor */
#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
#define SG_PINMON2 (SG_DBG_BASE | 0x0108)
#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)