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Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

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UniPhier SoC updates for v2020.04 (2nd)

Denali NAND driver changes:
 - Set up more registers in denali-spl for SOCFPGA
 - Make clocks optional
 - Do not assert reset signals in the remove hook
 - associate SPARE_AREA_SKIP_BYTES with DT compatible
 - switch to UCLASS_MTD

UniPhier platform changes:
 - fix a bug in dram_init()
 - specify loadaddr for "source" command
This commit is contained in:
Tom Rini
2020-01-31 13:26:28 -05:00
parent 514d00e527 76cd7d47fb
commit 80e99adbe4
15 changed files with 65 additions and 113 deletions
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1
arch/arm/Kconfig
View File

@@ -1548,6 +1548,7 @@ config ARCH_UNIPHIER
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_MTD
select DM_RESET
select DM_SERIAL
select DM_USB

2
arch/arm/mach-uniphier/board_init.c
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@@ -40,7 +40,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
.soc_id = UNIPHIER_LD4_ID,
.sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
@@ -56,7 +55,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
.soc_id = UNIPHIER_SLD8_ID,
.sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)

4
arch/arm/mach-uniphier/clk/Makefile
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@@ -11,9 +11,9 @@ obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
else
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-ld4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-ld4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o

32
arch/arm/mach-uniphier/clk/clk-ld4.c
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@@ -1,32 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
void uniphier_ld4_clk_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
writel(tmp, sc_base + SC_RSTCTRL);
readl(sc_base + SC_RSTCTRL); /* dummy read */
/* provide clocks */
tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
writel(tmp, sc_base + SC_CLKCTRL);
readl(sc_base + SC_CLKCTRL); /* dummy read */
}

14
arch/arm/mach-uniphier/clk/clk-pro4.c
View File

@@ -12,36 +12,26 @@
void uniphier_pro4_clk_init(void)
{
#ifdef CONFIG_USB_DWC3_UNIPHIER
u32 tmp;
/* deassert reset */
tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
writel(tmp, sc_base + SC_RSTCTRL);
readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
writel(tmp, sc_base + SC_RSTCTRL2);
readl(sc_base + SC_RSTCTRL2); /* dummy read */
#endif
/* provide clocks */
tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
writel(tmp, sc_base + SC_CLKCTRL);
readl(sc_base + SC_CLKCTRL); /* dummy read */
#endif
}

14
arch/arm/mach-uniphier/clk/clk-pro5.c
View File

@@ -10,35 +10,25 @@
void uniphier_pro5_clk_init(void)
{
#ifdef CONFIG_USB_DWC3_UNIPHIER
u32 tmp;
/* deassert reset */
tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
writel(tmp, sc_base + SC_RSTCTRL);
readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
writel(tmp, sc_base + SC_RSTCTRL2);
readl(sc_base + SC_RSTCTRL2); /* dummy read */
#endif
/* provide clocks */
tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
writel(tmp, sc_base + SC_CLKCTRL);
readl(sc_base + SC_CLKCTRL); /* dummy read */
#endif
}

14
arch/arm/mach-uniphier/clk/clk-pxs2.c
View File

@@ -11,20 +11,15 @@
void uniphier_pxs2_clk_init(void)
{
#ifdef CONFIG_USB_DWC3_UNIPHIER
u32 tmp;
/* deassert reset */
tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
writel(tmp, sc_base + SC_RSTCTRL);
readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
writel(tmp, sc_base + SC_RSTCTRL2);
@@ -33,17 +28,12 @@ void uniphier_pxs2_clk_init(void)
tmp = readl(sc_base + SC_RSTCTRL6);
tmp |= 0x37;
writel(tmp, sc_base + SC_RSTCTRL6);
#endif
/* provide clocks */
tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
writel(tmp, sc_base + SC_CLKCTRL);
readl(sc_base + SC_CLKCTRL); /* dummy read */
#endif
}

7
arch/arm/mach-uniphier/dram_init.c
View File

@@ -248,12 +248,7 @@ int dram_init(void)
max_size = (1ULL << 32) - dram_map[i].base;
if (dram_map[i].size > max_size) {
gd->ram_size += max_size;
break;
}
gd->ram_size += dram_map[i].size;
gd->ram_size = min(dram_map[i].size, max_size);
if (!valid_bank_found)
gd->ram_base = dram_map[i].base;

1
arch/arm/mach-uniphier/init.h
View File

@@ -90,7 +90,6 @@ void uniphier_ld11_pll_init(void);
void uniphier_ld20_pll_init(void);
void uniphier_pxs3_pll_init(void);
void uniphier_ld4_clk_init(void);
void uniphier_pro4_clk_init(void);
void uniphier_pro5_clk_init(void);
void uniphier_pxs2_clk_init(void);