Implement hard SPI driver on MPC8349EMDS
This patch implements the fsl_spi driver on the MPC8349EMDS evaluation board. This board has an ST M25P40 4Mbit EEPROM on its SPI bus Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -27,6 +27,7 @@
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#include <spi.h>
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#include <spd.h>
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#include <miiphy.h>
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#if defined(CONFIG_SPD_EEPROM)
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@ -251,6 +252,34 @@ void sdram_init(void)
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}
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#endif
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/*
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* The following are used to control the SPI chip selects for the SPI command.
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*/
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#ifdef CONFIG_HARD_SPI
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#define SPI_CS_MASK 0x80000000
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void spi_eeprom_chipsel(int cs)
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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if(cs)
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iopd->dat &= ~SPI_CS_MASK;
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else
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iopd->dat |= SPI_CS_MASK;
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}
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/*
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* The SPI command uses this table of functions for controlling the SPI
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* chip selects.
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*/
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spi_chipsel_type spi_chipsel[] = {
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spi_eeprom_chipsel,
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};
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int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
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#endif /* CONFIG_HARD_SPI */
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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@ -355,6 +355,16 @@
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#define CFG_I2C_OFFSET 0x3000
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#define CFG_I2C2_OFFSET 0x3100
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/* SPI */
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#define CONFIG_HARD_SPI /* SPI with hardware support*/
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#undef CONFIG_SOFT_SPI /* SPI bit-banged */
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#define CONFIG_FSL_SPI
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/* GPIOs. Used as SPI chip selects */
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#define CFG_GPIO1_PRELIM
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#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
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#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */
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/* TSEC */
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#define CFG_TSEC1_OFFSET 0x24000
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#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
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