ppc: xilinx-ppc4xx: Port to DM serial

xilinx_uartlite has been ported to DM, this patch makes the
xilinx-ppc405-generic and the xilinx-ppc440-generic boards use the new
DM driver.

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ricardo Ribalda Delgado
2016-01-26 11:24:19 +01:00
committed by Michal Simek
parent 5af0855670
commit 80cce2629b
9 changed files with 37 additions and 24 deletions

View File

@@ -46,3 +46,7 @@ void __get_sys_info(sys_info_t *sysInfo)
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
int get_serial_clock(void){
return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
}

View File

@@ -19,7 +19,6 @@
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif

View File

@@ -39,3 +39,7 @@ void __get_sys_info(sys_info_t *sysInfo)
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
int get_serial_clock(void){
return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
}

View File

@@ -17,7 +17,6 @@
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif