- MediaTek updates - xhci fixes - dwc2 stm32 compatible update
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commit
80c7e4cf76
@ -228,6 +228,3 @@
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resets = <&rcc UART8_R>;
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};
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&usbotg_hs {
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compatible = "st,stm32mp1-hsotg", "snps,dwc2";
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};
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@ -25,6 +25,10 @@ Required properties:
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Optional properties:
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- vbus-supply : reference to the VBUS regulator;
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- mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
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bit1 for u3port1, ... etc;
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- mediatek,u2p-dis-msk : mask to disable u2ports, bit0 for u2port0,
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bit1 for u2port1, ... etc;
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Example:
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xhci: usb@1a0c0000 {
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@ -1176,7 +1176,7 @@ static int dwc2_udc_otg_remove(struct udevice *dev)
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static const struct udevice_id dwc2_udc_otg_ids[] = {
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{ .compatible = "snps,dwc2" },
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{ .compatible = "brcm,bcm2835-usb" },
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{ .compatible = "st,stm32mp1-hsotg",
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{ .compatible = "st,stm32mp15-hsotg",
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.data = (ulong)dwc2_set_stm32mp1_hsotg_params },
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{},
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};
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@ -61,10 +61,13 @@ struct mtk_xhci {
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struct phy_bulk phys;
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int num_u2ports;
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int num_u3ports;
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u32 u3p_dis_msk;
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u32 u2p_dis_msk;
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};
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static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
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{
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int u3_ports_disabed = 0;
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u32 value;
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u32 check_val;
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int ret;
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@ -73,15 +76,23 @@ static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
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/* power on host ip */
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clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
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/* power on and enable all u3 ports */
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/* power on and enable u3 ports except skipped ones */
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for (i = 0; i < mtk->num_u3ports; i++) {
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if (BIT(i) & mtk->u3p_dis_msk) {
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u3_ports_disabed++;
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continue;
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}
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clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i),
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CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
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CTRL_U3_PORT_HOST_SEL);
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}
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/* power on and enable all u2 ports */
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/* power on and enable u2 ports except skipped ones */
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for (i = 0; i < mtk->num_u2ports; i++) {
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if (BIT(i) & mtk->u2p_dis_msk)
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continue;
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clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i),
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CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
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CTRL_U2_PORT_HOST_SEL);
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@ -94,7 +105,7 @@ static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
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check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
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STS1_SYS125_RST | STS1_XHCI_RST;
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if (mtk->num_u3ports)
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if (mtk->num_u3ports > u3_ports_disabed)
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check_val |= STS1_U3_MAC_RST;
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ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value,
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@ -176,6 +187,12 @@ static int xhci_mtk_ofdata_get(struct mtk_xhci *mtk)
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if (ret)
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debug("can't get vbus regulator %d!\n", ret);
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/* optional properties to disable ports, ignore the error */
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dev_read_u32(dev, "mediatek,u3p-dis-msk", &mtk->u3p_dis_msk);
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dev_read_u32(dev, "mediatek,u2p-dis-msk", &mtk->u2p_dis_msk);
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dev_info(dev, "ports disabled mask: u3p-0x%x, u2p-0x%x\n",
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mtk->u3p_dis_msk, mtk->u2p_dis_msk);
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return 0;
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}
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@ -13,8 +13,8 @@
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#include <usb.h>
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#include <usb/xhci.h>
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static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
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struct xhci_hcor **ret_hcor)
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static int xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
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struct xhci_hcor **ret_hcor)
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{
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struct xhci_hccr *hccr;
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struct xhci_hcor *hcor;
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@ -22,6 +22,11 @@ static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
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hccr = (struct xhci_hccr *)dm_pci_map_bar(dev,
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PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
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if (!hccr) {
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printf("xhci-pci init cannot map PCI mem bar\n");
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return -EIO;
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}
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hcor = (struct xhci_hcor *)((uintptr_t) hccr +
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HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
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@ -35,14 +40,18 @@ static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
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dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MASTER;
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dm_pci_write_config32(dev, PCI_COMMAND, cmd);
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return 0;
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}
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static int xhci_pci_probe(struct udevice *dev)
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{
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struct xhci_hccr *hccr;
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struct xhci_hcor *hcor;
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int ret;
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xhci_pci_init(dev, &hccr, &hcor);
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ret = xhci_pci_init(dev, &hccr, &hcor);
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if (ret)
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return ret;
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return xhci_register(dev, hccr, hcor);
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}
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@ -723,8 +723,8 @@ again:
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return -ETIMEDOUT;
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}
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if ((uintptr_t)(le64_to_cpu(event->trans_event.buffer))
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!= (uintptr_t)last_transfer_trb_addr) {
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if ((uintptr_t)(le64_to_cpu(event->trans_event.buffer)) !=
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(uintptr_t)virt_to_phys(last_transfer_trb_addr)) {
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available_length -=
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(int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len));
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xhci_acknowledge_event(ctrl);
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