board: sl28: add SATA support
Enable SATA support. Although not supported by the usual SATA pins on the SMARC baseboard connector, SATA mode is supported on a PCIe lane. This way one can use a mSATA card in a Mini PCI slot. We need to invert the received data because in this mode the polarity of the SerDes lane is swapped. Provide a fixup in board_early_init_f() for the SPL. board_early_init_f() is then not common between SPL and u-boot proper anymore, thus common.c is removed, as it just contained said function. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -172,6 +172,10 @@
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};
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};
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&sata {
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status = "okay";
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};
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&serial0 {
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status = "okay";
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};
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@ -4,7 +4,7 @@ ifndef CONFIG_SPL_BUILD
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obj-y += sl28.o cmds.o
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endif
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obj-y += common.o ddr.o
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obj-y += ddr.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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@ -1,10 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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int board_early_init_f(void)
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{
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fsl_lsch3_early_init_f();
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return 0;
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}
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@ -19,6 +19,12 @@
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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fsl_lsch3_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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if (CONFIG_IS_ENABLED(FSL_CAAM))
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@ -3,10 +3,36 @@
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#include <common.h>
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#include <asm/io.h>
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#include <asm/spl.h>
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#include <asm/arch-fsl-layerscape/fsl_serdes.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#define DCFG_RCWSR25 0x160
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#define GPINFO_HW_VARIANT_MASK 0xff
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#define SERDES_LNDGCR0 0x1ea08c0
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#define LNDGCR0_PROTS_MASK GENMASK(11, 7)
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#define LNDGCR0_PROTS_SATA (0x2 << 7)
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#define SERDES_LNDGCR1 0x1ea08c4
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#define LNDGCR1_RDAT_INV BIT(31)
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/*
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* On this board the SMARC PCIe lane D might be switched to SATA mode. This
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* makes sense if this lane is connected to a Mini PCI slot and a mSATA card
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* is plugged in. In this case, the RX pair is swapped and we need to invert
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* the received data.
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*/
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static void fixup_sata_rx_polarity(void)
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{
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u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK;
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u32 tmp;
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if (prot == LNDGCR0_PROTS_SATA) {
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tmp = in_le32(SERDES_LNDGCR1);
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tmp |= LNDGCR1_RDAT_INV;
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out_le32(SERDES_LNDGCR1, tmp);
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}
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}
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int sl28_variant(void)
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{
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return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
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@ -34,3 +60,11 @@ void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = BOOT_DEVICE_SPI;
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}
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int board_early_init_f(void)
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{
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fixup_sata_rx_polarity();
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fsl_lsch3_early_init_f();
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return 0;
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}
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@ -62,6 +62,7 @@ CONFIG_DM=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_FSL_CAAM=y
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CONFIG_SYS_FSL_DDR3=y
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CONFIG_DM_I2C=y
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@ -93,6 +93,7 @@
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func(MMC, mmc, 1) \
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func(NVME, nvme, 0) \
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func(USB, usb, 0) \
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func(SCSI, scsi, 0) \
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func(DHCP, dhcp, 0) \
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func(PXE, pxe, 0)
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#include <config_distro_bootcmd.h>
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