leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value

Browse Source 
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
2015-02-16 10:15:56 +05:30
committed by Tom Rini
parent aa8ac43645
commit 802bb57a58
4 changed files with 14 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
board/ti/beagle_x15/board.c
View File

@@ -47,7 +47,8 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x00001035,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
@@ -103,7 +104,8 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x00001035,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,