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mxs: mmc: Fix MMC reset on iMX23

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This does the same reset mask as done in v3.7 Linux kernel code.
The block is properly configured for MMC operation that way.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Otavio Salvador 2013-01-22 15:01:02 +00:00 committed by Stefano Babic
parent f3801e2b9b
commit 8000d8a826
1 changed files with 11 additions and 5 deletions
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16
drivers/mmc/mxsmmc.c
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@ -334,11 +334,17 @@ static int mxsmmc_init(struct mmc *mmc)
/* Reset SSP */ /* Reset SSP */
mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
/* 8 bits word length in MMC mode */ /* Reconfigure the SSP block for MMC operation */
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, writel(SSP_CTRL1_SSP_MODE_SD_MMC |
SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
SSP_CTRL1_DMA_ENABLE, SSP_CTRL1_DMA_ENABLE |
SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); SSP_CTRL1_POLARITY |
SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
SSP_CTRL1_DATA_CRC_IRQ_EN |
SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
SSP_CTRL1_RESP_ERR_IRQ_EN,
&ssp_regs->hw_ssp_ctrl1_set);
/* Set initial bit clock 400 KHz */ /* Set initial bit clock 400 KHz */
mxs_set_ssp_busclock(priv->id, 400); mxs_set_ssp_busclock(priv->id, 400);