From 12218c1ff41befedd78ed8cfa902f2cc25d05c88 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 20 Jan 2021 21:37:56 +0100 Subject: [PATCH 01/15] cmd: CMD_ACPI depends on ACPIGEN Trying to compile qemu-x86_64_defconfig with CONFIG_CMD_ACPI=y and CONFIG_ACPIGEN=n fails with ld.bfd: cmd/built-in.o: in function `do_acpi_items': cmd/acpi.c:162: undefined reference to `acpi_dump_items' Add the missing configuration dependency. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- cmd/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 0625ee4050..928a2a0a2d 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -84,7 +84,8 @@ menu "Info commands" config CMD_ACPI bool "acpi" - default y if ACPIGEN + depends on ACPIGEN + default y help List and dump ACPI tables. ACPI (Advanced Configuration and Power Interface) is used mostly on x86 for providing information to the From 9edf20f15649cda83214b3b6dc90ca9acff45abb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 13 Jan 2021 20:29:45 -0700 Subject: [PATCH 02/15] x86: tsc_timer: Correct overflow in __udelay() At present long delays such as msleep(2000) can cause an overflow in this function. There is no need for this, since it already uses a 64-bit int. Add a cast to correct this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/timer/tsc_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 706d52b830..7d0fc66cc7 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -372,7 +372,7 @@ void __udelay(unsigned long usec) u64 now = get_ticks(); u64 stop; - stop = now + usec * get_tbclk_mhz(); + stop = now + (u64)usec * get_tbclk_mhz(); while ((int64_t)(stop - get_ticks()) > 0) #if defined(CONFIG_QEMU) && defined(CONFIG_SMP) From 0751cda5745efcff1a4bfc70c42bab380901b0b8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 13 Jan 2021 20:29:53 -0700 Subject: [PATCH 03/15] x86: coral: Add a devicetree node for eMMC Add a node for this so we can indicate that it is does not require any ACPI code. Signed-off-by: Simon Glass Reviewed-by: Jaehoon Chung Reviewed-by: Bin Meng --- arch/x86/dts/chromebook_coral.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 9319123c0c..2ffe3b423c 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -575,6 +575,12 @@ acpi,name = "SDCD"; }; + emmc: emmc@1c,0 { + reg = <0x0000e000 0 0 0 0>; + compatible = "intel,apl-emmc"; + non-removable; + }; + pch: pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,apl-pch"; From 8a655272d7b440dc3eeda598eb2d05819c0f75c2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 23 Jan 2021 11:08:38 -0700 Subject: [PATCH 04/15] acpi: Tidy up documentation for struct acpi_gpio Some comments were provided after this patch was applied. Address them. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/acpi/acpi_device.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h index ed4acd912a..2c8846250b 100644 --- a/include/acpi/acpi_device.h +++ b/include/acpi/acpi_device.h @@ -171,10 +171,11 @@ enum acpi_gpio_polarity { * @io_restrict: I/O restriction setting * @polarity: GPIO polarity * - * Note that GpioIo doesn't have any means of Active Low / High setting, so a - * _DSD must be provided to mitigate this. + * Note that GpioIo() doesn't have any means of Active Low / High setting, so a + * _DSD must be provided to mitigate this. This parameter does not make sense + * for GpioInt() since it has its own means to define it. * - * GpioIo doesn't properly communicate the initial state of the output pin, + * GpioIo() doesn't properly communicate the initial state of the output pin, * thus Linux assumes the simple rule: * * Pull Bias Polarity Requested... @@ -184,7 +185,7 @@ enum acpi_gpio_polarity { * assuming non-active (Polarity = !Pull Bias) * * Down Low as low, assuming active - * Down High as high, assuming non-active + * Down High as low, assuming non-active * Up Low as high, assuming non-active * Up High as high, assuming active * From 6754393d260cf779a1c441a58c305a6b62e6a82d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:02 -0700 Subject: [PATCH 05/15] x86: acpi_gpe: Update driver name to match devicetree Use a driver name in line with the compatible string so that of-platdata can use this driver. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/acpi_gpe.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c index 83128c33c2..da01e71335 100644 --- a/arch/x86/cpu/acpi_gpe.c +++ b/arch/x86/cpu/acpi_gpe.c @@ -4,6 +4,8 @@ * Written by Simon Glass */ +#define LOG_CATEGORY UCLASS_IRQ + #include #include #include @@ -102,8 +104,8 @@ static const struct udevice_id acpi_gpe_ids[] = { { } }; -U_BOOT_DRIVER(acpi_gpe_drv) = { - .name = "acpi_gpe", +U_BOOT_DRIVER(intel_acpi_gpe) = { + .name = "intel_acpi_gpe", .id = UCLASS_IRQ, .of_match = acpi_gpe_ids, .ops = &acpi_gpe_ops, From 86c372af1abd02f6d81c287159e5d80bb27b8ae4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:03 -0700 Subject: [PATCH 06/15] x86: spl: Add a function to find the text base It is useful to know the TEXT_BASE value for the image being loaded in TPL/SPL. Add a new spl_get_image_text_base() function to handle this. Make use of this in the x86 SPL handler, instead of having the logic there. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- common/spl/spl.c | 6 ++++++ include/spl.h | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/common/spl/spl.c b/common/spl/spl.c index 8cb6f3d531..cdd7b05f27 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -144,6 +144,12 @@ ulong spl_get_image_size(void) binman_sym(ulong, u_boot_any, size); } +ulong spl_get_image_text_base(void) +{ + return spl_phase() == PHASE_TPL ? CONFIG_SPL_TEXT_BASE : + CONFIG_SYS_TEXT_BASE; +} + /* * Weak default function for board specific cleanup/preparation before * Linux boot. Some boards/platforms might not need it, so just provide diff --git a/include/spl.h b/include/spl.h index faffeb519a..e172500b5f 100644 --- a/include/spl.h +++ b/include/spl.h @@ -254,6 +254,16 @@ ulong spl_get_image_pos(void); */ ulong spl_get_image_size(void); +/** + * spl_get_image_text_base() - get the text base of the next phase + * + * This returns the address that the next stage is linked to run at, i.e. + * CONFIG_SPL_TEXT_BASE or CONFIG_SYS_TEXT_BASE + * + * @return text-base address + */ +ulong spl_get_image_text_base(void); + /** * spl_load_simple_fit_skip_processing() - Hook to allow skipping the FIT * image processing during spl_load_simple_fit(). From 0b2bedbc6d02d9b9563b40a2b7e39fec6e9bf07c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:04 -0700 Subject: [PATCH 07/15] x86: apl: Enhance debugging in the SPL loader Move to log_debug() and make use of the new SPL function to find the text base. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/apollolake/spl.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c index 8991d5e648..f2d25734c6 100644 --- a/arch/x86/cpu/apollolake/spl.c +++ b/arch/x86/cpu/apollolake/spl.c @@ -3,6 +3,8 @@ * Copyright 2019 Google LLC */ +#define LOG_CATEGORY LOGC_BOOT + #include #include #include @@ -33,12 +35,11 @@ static int rom_load_image(struct spl_image_info *spl_image, int ret; spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ - spl_image->entry_point = spl_phase() == PHASE_TPL ? - CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE; + spl_image->entry_point = spl_get_image_text_base(); spl_image->load_addr = spl_image->entry_point; spl_image->os = IH_OS_U_BOOT; spl_image->name = "U-Boot"; - debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size); + log_debug("Reading from mapped SPI %lx, size %lx\n", spl_pos, spl_size); if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) { ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev); @@ -56,7 +57,8 @@ static int rom_load_image(struct spl_image_info *spl_image, return ret; } spl_pos += map_base & ~0xff000000; - debug(", base %lx, pos %lx\n", map_base, spl_pos); + log_debug(", base %lx, pos %lx, load %lx\n", map_base, spl_pos, + spl_image->load_addr); bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size); cpu_flush_l1d_to_l2(); @@ -121,7 +123,7 @@ static int spl_fast_spi_load_image(struct spl_image_info *spl_image, spl_image->os = IH_OS_U_BOOT; spl_image->name = "U-Boot"; spl_pos &= ~0xff000000; - debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size); + log_debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size); ret = spi_flash_read_dm(dev, spl_pos, spl_size, (void *)spl_image->load_addr); cpu_flush_l1d_to_l2(); From 37c664e82534ad84d2f7c06ce7d6459fa6bd24ae Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:05 -0700 Subject: [PATCH 08/15] x86: Make sure the SPL image ends on a suitable boundary The part of U-Boot that actually ends up in u-boot-nodtb.bin is not built with any particular alignment. It ends at the start of the BSS section. The BSS section selects its own alignment, which may larger. This means that there can be a gap of a few bytes between the image ending and BSS starting. Since u-boot.bin is build by joining u-boot-nodtb.bin and u-boot.dtb (with perhaps some padding for BSS), the expected result is not obtained. U-Boot uses the end of BSS to find the devicetree, so this means that it cannot be found. Add 32-byte alignment of BSS so that the image size is correct and appending the devicetree will place it at the end of BSS. Example SPL output without this patch: Sections: Idx Name Size VMA LMA File off Algn 0 .text 000142a1 fef40000 fef40000 00001000 2**4 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE 1 .u_boot_list 000014a4 fef542a8 fef542a8 000152a8 2**3 CONTENTS, ALLOC, LOAD, RELOC, DATA 2 .rodata 0000599c fef55760 fef55760 00016760 2**5 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA 3 .data 00000970 fef5b100 fef5b100 0001c100 2**5 CONTENTS, ALLOC, LOAD, RELOC, DATA 4 .binman_sym_table 00000020 fef5ba70 fef5ba70 0001ca70 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .bss 00000060 fef5baa0 fef5baa0 00000000 2**5 ALLOC You can see that .bss is aligned to 2**5 (32 bytes). This is because of the mallinfo struct in dlmalloc.c: 17 .bss.current_mallinfo 00000028 00000000 00000000 000004c0 2**5 ALLOC In this case the size of u-boot-spl-nodtb.bin is 0x1ba90. This matches up with the _image_binary_end symbol: fef5ba90 g .binman_sym_table 00000000 _image_binary_end But BSS starts 16 bytes later, at 0xfef5baa0, due to the 32-byte alignment. So we must align _image_binary_end to a 32-byte boundary. This forces the binary size to be 0x1baa0, i.e. ending at the start of bss, as expected. Note that gcc reports __BIGGEST_ALIGNMENT__ of 16 on this build, even though it generates an object file with a member that requests 32-byte alignment. The current_mallinfo struct is 40 bytes in size. Increasing the struct to 68 bytes (i.e. just above a 64-byte boundary) does not cause the alignment to go above 32 bytes. So it seems that 32 bytes is the maximum alignment at present. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: add more details in the commit message to help people understand] Signed-off-by: Bin Meng --- arch/x86/cpu/u-boot-spl.lds | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds index e6c22895b3..ead4f380e7 100644 --- a/arch/x86/cpu/u-boot-spl.lds +++ b/arch/x86/cpu/u-boot-spl.lds @@ -43,6 +43,16 @@ SECTIONS __binman_sym_start = .; KEEP(*(SORT(.binman_sym*))); __binman_sym_end = .; + + /* + * Force 32-byte alignment so that it lines up with the start of + * bss, which may have up to 32-byte alignment. This ensures + * that the end of the .bin file matches up with + * _image_binary_end or __bss_end - see board_fdt_blob_setup(). + * The alignment of BSS depends on what is in it, so can range + * from 4 to 32 bytes. + */ + . = ALIGN(32); } _image_binary_end = .; From 76baecf6702bfb6ccf9fb316edc4b6737fa6602c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:06 -0700 Subject: [PATCH 09/15] x86: spl: Make moving BSS conditional At present BSS is always placed in SDRAM. If a separate BSS is not in use this means that BSS doesn't work as expected. Make the setting conditional on the SEPARATE_BSS option. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/u-boot-spl.lds | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds index ead4f380e7..b82e53ab12 100644 --- a/arch/x86/cpu/u-boot-spl.lds +++ b/arch/x86/cpu/u-boot-spl.lds @@ -57,7 +57,9 @@ SECTIONS _image_binary_end = .; +#if CONFIG_IS_ENABLED(SEPARATE_BSS) . = 0x120000; +#endif .bss (OVERLAY) : { __bss_start = .; *(.bss*) From f82438948f649c33d775badd099869b0652ecc41 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:07 -0700 Subject: [PATCH 10/15] x86: Update Chromium OS GNVS names The Global Non-Volatile Storage struct has some fields with particular meanings. Rename these to make things easier to follow. Also add a few more boot flags. GNVS should not be confused with GNVQ (Going Nowhere Very Quickly). Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/intel_gnvs.h | 34 +++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h index 7f9f101371..69a20812e5 100644 --- a/arch/x86/include/asm/intel_gnvs.h +++ b/arch/x86/include/asm/intel_gnvs.h @@ -9,6 +9,7 @@ #ifndef _INTEL_GNVS_H_ #define _INTEL_GNVS_H_ +#include /* * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset * 0x100 - 0x1000. When defining acpi_global_nvs, use check_member @@ -18,6 +19,11 @@ */ #define GNVS_CHROMEOS_ACPI_OFFSET 0x100 +enum { + BOOT_REASON_OTHER = 0, + BOOT_REASON_S3DIAG = 9 +}; + enum { CHSW_RECOVERY_X86 = BIT(1), CHSW_RECOVERY_EC = BIT(2), @@ -25,6 +31,22 @@ enum { CHSW_FIRMWARE_WP = BIT(9), }; +enum { + RECOVERY_REASON_NONE = 0, + RECOVERY_REASON_ME = 1 +}; + +enum { + ACTIVE_ECFW_RO = 0, + ACTIVE_ECFW_RW = 1 +}; + +enum { + BINF_RECOVERY = 0, + BINF_RW_A = 1, + BINF_RW_B = 2 +}; + enum { FIRMWARE_TYPE_AUTO_DETECT = -1, FIRMWARE_TYPE_RECOVERY = 0, @@ -40,14 +62,14 @@ struct __packed chromeos_acpi_gnvs { u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */ u32 activeec_fw; /* 08 (0=RO, 1=RW) */ u16 switches; /* 0c CHSW */ - u8 vbt4[256]; /* 0e HWID */ - u8 vbt5[64]; /* 10e FWID */ - u8 vbt6[64]; /* 14e FRID - 275 */ + u8 hwid[256]; /* 0e HWID */ + u8 fwid[64]; /* 10e FWID */ + u8 frid[64]; /* 14e FRID - 275 */ u32 main_fw_type; /* 18e (2 = developer mode) */ - u32 vbt8; /* 192 recovery reason */ - u32 vbt9; /* 196 fmap base address */ + u32 recovery_reason; /* 192 recovery reason */ + u32 fmap_base; /* 196 fmap base address */ u8 vdat[3072]; /* 19a VDAT space filled by verified boot */ - u32 vbt10; /* d9a smbios bios version */ + u32 fwid_ptr; /* d9a smbios bios version */ u32 mehh[8]; /* d9e management engine hash */ u32 ramoops_base; /* dbe ramoops base address */ u32 ramoops_len; /* dc2 ramoops length */ From 577c4ad0550825fa94c44ebca23523f05faecf17 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:08 -0700 Subject: [PATCH 11/15] x86: zimage: Allow dumping the image from outside the module At present it is possible to dump an image within the zimage command, but it is also useful to be able to dump it from elsewhere, for example in a loader that has special handling for the different zimage stages. Export this feature as a new function. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/zimage.h | 10 ++++++++++ arch/x86/lib/zimage.c | 23 +++++++++++++++-------- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 64c0e6e857..6679767d16 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -62,6 +62,16 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, ulong initrd_addr, ulong initrd_size, ulong cmdline_force); +/** + * zimage_dump() - Dump the metadata of a zimage + * + * This shows all available information in a zimage that has been loaded. + * + * @base_ptr: Pointer to the boot parameters, typically at address + * DEFAULT_SETUP_BASE + */ +void zimage_dump(struct boot_params *base_ptr); + void setup_video(struct screen_info *screen_info); void setup_efi_info(struct efi_info *efi_info); diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 708025b207..3e9ee12400 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -600,19 +600,12 @@ static void show_loader(struct setup_header *hdr) printf("\n"); } -int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +void zimage_dump(struct boot_params *base_ptr) { - struct boot_params *base_ptr = state.base_ptr; struct setup_header *hdr; const char *version; int i; - if (argc > 1) - base_ptr = (void *)simple_strtoul(argv[1], NULL, 16); - if (!base_ptr) { - printf("No zboot setup_base\n"); - return CMD_RET_FAILURE; - } printf("Setup located at %p:\n\n", base_ptr); print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr); @@ -688,6 +681,20 @@ int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) print_num("Handover offset", hdr->handover_offset); if (get_boot_protocol(hdr, false) >= 0x215) print_num("Kernel info offset", hdr->kernel_info_offset); +} + +static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct boot_params *base_ptr = state.base_ptr; + + if (argc > 1) + base_ptr = (void *)simple_strtoul(argv[1], NULL, 16); + if (!base_ptr) { + printf("No zboot setup_base\n"); + return CMD_RET_FAILURE; + } + zimage_dump(base_ptr); return 0; } From 06c085c0d2a1ae33b1772d04dec9b1f66af12f14 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:09 -0700 Subject: [PATCH 12/15] x86: zimage: Improve command-line debug handling At present if the command line is very long it is truncated by the printf() statement, which works within a limited buffer. Use puts() instead. Also show better debugging with the command-line setup fails. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/zimage.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 3e9ee12400..602788e016 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -109,8 +109,11 @@ static void build_command_line(char *command_line, int auto_boot) if (env_command_line) strcat(command_line, env_command_line); - - printf("Kernel command line: \"%s\"\n", command_line); +#ifdef DEBUG + printf("Kernel command line:"); + puts(command_line); + printf("\n"); +#endif } static int kernel_magic_ok(struct setup_header *hdr) @@ -354,7 +357,8 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, build_command_line(cmd_line, auto_boot); ret = bootm_process_cmdline(cmd_line, max_size, BOOTM_CL_ALL); if (ret) { - printf("Cmdline setup failed (err=%d)\n", ret); + printf("Cmdline setup failed (max_size=%x, bootproto=%x, err=%d)\n", + max_size, bootproto, ret); return ret; } printf("Kernel command line: \""); From 02840ca1b0e90424d7546cb75117463c873eecc6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:10 -0700 Subject: [PATCH 13/15] x86: spl: Clear BSS unconditionally This should be done even if not using TPL, since BSS may be in use or boards that only use SPL. Fix it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index cf22fa2d7b..6699de49c6 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -115,8 +115,8 @@ static int x86_spl_init(void) } #ifndef CONFIG_SYS_COREBOOT -# ifndef CONFIG_TPL memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); +# ifndef CONFIG_TPL /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ ret = interrupt_init(); From 3138e4603c39a76fa52b38d9ed52cd7e7277c45d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 10:06:11 -0700 Subject: [PATCH 14/15] x86: tpl: Show next stage being booted Enhance the debugging to show the next stage being booted as well as a dump of the start of the image. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/tpl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 04ff32277f..c84a0c9bc7 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -111,7 +111,12 @@ int spl_spi_load_image(void) void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { - debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point); + debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()), + (ulong)spl_image->entry_point); +#ifdef DEBUG + print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1, + 0x20, 0); +#endif jump_to_spl(spl_image->entry_point); hang(); } From 77f898d04095cdccb69c476ba0aa19f257fca64d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 31 Jan 2021 09:17:07 -0700 Subject: [PATCH 15/15] x86: Reduce size of samus image With the recent addition of ACPI generation, the image size has got beyond its current limit. Samus does not actually use this, nor x86 emulation for PCI ROMs, so disable both features. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- configs/chromebook_samus_defconfig | 1 + include/configs/chromebook_samus.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index c0d2b04ccd..71b5f8bdfe 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -54,6 +54,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y +# CONFIG_ACPIGEN is not set CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h index dfeede7e91..2fe3e72199 100644 --- a/include/configs/chromebook_samus.h +++ b/include/configs/chromebook_samus.h @@ -15,6 +15,9 @@ #include #include +/* We can rely on running natively, and this saves code size */ +#undef CONFIG_BIOSEMU + #undef CONFIG_STD_DEVICES_SETTINGS #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \