rk3288: sdram: auto-detect the capacity
Add support for rk3288 dram capacity auto detect, support DDR3 and LPDDR3, DDR2 is not supported. The program will automatically detect: - channel number - rank number - column address number - row address number The dts file do not need to describe those info after apply this patch. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
This commit is contained in:
Kever Yang
Simon Glass
parent
cd2f6b8b95
commit
7d6c78f573
@ -16,6 +16,11 @@ enum {
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};
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struct rk3288_sdram_channel {
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/*
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* bit width in address, eg:
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* 8 banks using 3 bit to address,
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* 2 cs using 1 bit to address.
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*/
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u8 rank;
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u8 col;
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u8 bk;
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@ -87,6 +92,16 @@ struct rk3288_base_params {
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u32 ddrconfig;
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u32 ddr_freq;
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u32 dramtype;
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/*
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* DDR Stride is address mapping for DRAM space
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* Stride Ch 0 range Ch1 range Total
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* 0x00 0-256MB 256MB-512MB 512MB
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* 0x05 0-1GB 0-1GB 1GB
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* 0x09 0-2GB 0-2GB 2GB
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* 0x0d 0-4GB 0-4GB 4GB
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* 0x17 N/A 0-4GB 4GB
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* 0x1a 0-4GB 4GB-8GB 8GB
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*/
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u32 stride;
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u32 odt;
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};
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@ -57,6 +57,10 @@ struct rk3288_sdram_params {
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struct regmap *map;
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};
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#define TEST_PATTEN 0x5aa5f00f
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#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
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#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
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#ifdef CONFIG_SPL_BUILD
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static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
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{
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@ -214,7 +218,7 @@ static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel,
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}
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static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
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const struct rk3288_sdram_params *sdram_params,
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struct rk3288_sdram_params *sdram_params,
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struct rk3288_grf *grf)
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{
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unsigned int burstlen;
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@ -264,7 +268,7 @@ static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
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}
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static void phy_cfg(const struct chan_info *chan, u32 channel,
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const struct rk3288_sdram_params *sdram_params)
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struct rk3288_sdram_params *sdram_params)
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{
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struct rk3288_ddr_publ *publ = chan->publ;
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struct rk3288_msch *msch = chan->msch;
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@ -446,7 +450,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
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}
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static int data_training(const struct chan_info *chan, u32 channel,
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const struct rk3288_sdram_params *sdram_params)
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struct rk3288_sdram_params *sdram_params)
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{
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unsigned int j;
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int ret = 0;
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@ -549,7 +553,7 @@ static void move_to_access_state(const struct chan_info *chan)
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}
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static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
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const struct rk3288_sdram_params *sdram_params)
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struct rk3288_sdram_params *sdram_params)
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{
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struct rk3288_ddr_publ *publ = chan->publ;
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@ -563,7 +567,7 @@ static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
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}
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static void dram_all_config(const struct dram_info *dram,
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const struct rk3288_sdram_params *sdram_params)
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struct rk3288_sdram_params *sdram_params)
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{
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unsigned int chan;
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u32 sys_reg = 0;
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@ -589,9 +593,191 @@ static void dram_all_config(const struct dram_info *dram,
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writel(sys_reg, &dram->pmu->sys_reg[2]);
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rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
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}
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const int ddrconf_table[] = {
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/* row col,bw */
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0,
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((1 << 4) | 1),
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((2 << 4) | 1),
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((3 << 4) | 1),
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((4 << 4) | 1),
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((1 << 4) | 2),
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((2 << 4) | 2),
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((3 << 4) | 2),
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((1 << 4) | 0),
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((2 << 4) | 0),
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((3 << 4) | 0),
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0,
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0,
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0,
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0,
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((4 << 4) | 2),
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};
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static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
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struct rk3288_sdram_params *sdram_params)
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{
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int reg;
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int need_trainig = 0;
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const struct chan_info *chan = &dram->chan[channel];
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struct rk3288_ddr_publ *publ = chan->publ;
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if (-1 == data_training(chan, channel, sdram_params)) {
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reg = readl(&publ->datx8[0].dxgsr[0]);
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/* Check the result for rank 0 */
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if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
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debug("data training fail!\n");
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return -EIO;
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} else if ((channel == 1) &&
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(reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
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sdram_params->num_channels = 1;
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}
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/* Check the result for rank 1 */
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if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
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sdram_params->ch[channel].rank = 1;
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clrsetbits_le32(&publ->pgcr, 0xF << 18,
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sdram_params->ch[channel].rank << 18);
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need_trainig = 1;
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}
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reg = readl(&publ->datx8[2].dxgsr[0]);
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if (reg & (1 << 4)) {
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sdram_params->ch[channel].bw = 1;
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set_bandwidth_ratio(chan, channel,
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sdram_params->ch[channel].bw,
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dram->grf);
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need_trainig = 1;
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}
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}
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/* Assume the Die bit width are the same with the chip bit width */
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sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
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if (need_trainig &&
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(-1 == data_training(chan, channel, sdram_params))) {
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if (sdram_params->base.dramtype == LPDDR3) {
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ddr_phy_ctl_reset(dram->cru, channel, 1);
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udelay(10);
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ddr_phy_ctl_reset(dram->cru, channel, 0);
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udelay(10);
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}
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debug("2nd data training failed!");
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return -EIO;
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}
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return 0;
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}
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static int sdram_col_row_detect(struct dram_info *dram, int channel,
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struct rk3288_sdram_params *sdram_params)
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{
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int row, col;
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unsigned int addr;
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const struct chan_info *chan = &dram->chan[channel];
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struct rk3288_ddr_pctl *pctl = chan->pctl;
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struct rk3288_ddr_publ *publ = chan->publ;
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int ret = 0;
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/* Detect col */
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for (col = 11; col >= 9; col--) {
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writel(0, CONFIG_SYS_SDRAM_BASE);
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addr = CONFIG_SYS_SDRAM_BASE +
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(1 << (col + sdram_params->ch[channel].bw - 1));
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writel(TEST_PATTEN, addr);
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if ((readl(addr) == TEST_PATTEN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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break;
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}
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if (col == 8) {
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printf("Col detect error\n");
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ret = -EINVAL;
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goto out;
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} else {
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sdram_params->ch[channel].col = col;
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}
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move_to_config_state(publ, pctl);
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writel(4, &chan->msch->ddrconf);
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move_to_access_state(chan);
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/* Detect row*/
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for (row = 16; row >= 12; row--) {
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writel(0, CONFIG_SYS_SDRAM_BASE);
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addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
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writel(TEST_PATTEN, addr);
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if ((readl(addr) == TEST_PATTEN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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break;
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}
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if (row == 11) {
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printf("Row detect error\n");
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ret = -EINVAL;
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} else {
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sdram_params->ch[channel].cs1_row = row;
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sdram_params->ch[channel].row_3_4 = 0;
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debug("chn %d col %d, row %d\n", channel, col, row);
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sdram_params->ch[channel].cs0_row = row;
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}
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out:
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return ret;
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}
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static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params)
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{
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int i, tmp, size, ret = 0;
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tmp = sdram_params->ch[0].col - 9;
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tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
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tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4);
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size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
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for (i = 0; i < size; i++)
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if (tmp == ddrconf_table[i])
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break;
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if (i >= size) {
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printf("niu config not found\n");
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ret = -EINVAL;
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} else {
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sdram_params->base.ddrconfig = i;
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}
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return ret;
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}
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static int sdram_get_stride(struct rk3288_sdram_params *sdram_params)
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{
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int stride = -1;
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int ret = 0;
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long cap = sdram_params->num_channels * (1u <<
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(sdram_params->ch[0].cs0_row +
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sdram_params->ch[0].col +
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(sdram_params->ch[0].rank - 1) +
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sdram_params->ch[0].bw +
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3 - 20));
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switch (cap) {
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case 512:
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stride = 0;
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break;
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case 1024:
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stride = 5;
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break;
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case 2048:
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stride = 9;
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break;
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case 4096:
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stride = 0xd;
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break;
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default:
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stride = -1;
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printf("could not find correct stride, cap error!\n");
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ret = -EINVAL;
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break;
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}
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sdram_params->base.stride = stride;
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return ret;
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}
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static int sdram_init(struct dram_info *dram,
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const struct rk3288_sdram_params *sdram_params)
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struct rk3288_sdram_params *sdram_params)
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{
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int channel;
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int zqcr;
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@ -619,12 +805,14 @@ static int sdram_init(struct dram_info *dram,
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struct rk3288_ddr_pctl *pctl = chan->pctl;
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struct rk3288_ddr_publ *publ = chan->publ;
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/* map all the 4GB space to the current channel */
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if (channel)
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rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17);
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else
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rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a);
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phy_pctrl_reset(dram->cru, publ, channel);
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phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
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if (channel >= sdram_params->num_channels)
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continue;
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dfi_cfg(pctl, sdram_params->base.dramtype);
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pctl_cfg(channel, pctl, sdram_params, dram->grf);
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@ -658,16 +846,20 @@ static int sdram_init(struct dram_info *dram,
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udelay(1);
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}
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/* Using 32bit bus width for detect */
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sdram_params->ch[channel].bw = 2;
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set_bandwidth_ratio(chan, channel,
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sdram_params->ch[channel].bw, dram->grf);
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/*
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* set cs
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* set cs, using n=3 for detect
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* CS0, n=1
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* CS1, n=2
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* CS0 & CS1, n = 3
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*/
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sdram_params->ch[channel].rank = 2,
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clrsetbits_le32(&publ->pgcr, 0xF << 18,
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(sdram_params->ch[channel].rank | 1) << 18);
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/* DS=40ohm,ODT=155ohm */
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zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
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2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
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@ -693,16 +885,8 @@ static int sdram_init(struct dram_info *dram,
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}
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}
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if (-1 == data_training(chan, channel, sdram_params)) {
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if (sdram_params->base.dramtype == LPDDR3) {
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ddr_phy_ctl_reset(dram->cru, channel, 1);
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udelay(10);
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ddr_phy_ctl_reset(dram->cru, channel, 0);
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udelay(10);
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}
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debug("failed!");
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return -EIO;
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}
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/* Detect the rank and bit-width with data-training */
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sdram_rank_bw_detect(dram, channel, sdram_params);
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if (sdram_params->base.dramtype == LPDDR3) {
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u32 i;
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@ -710,12 +894,31 @@ static int sdram_init(struct dram_info *dram,
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for (i = 0; i < 17; i++)
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send_command_op(pctl, 1, MRR_CMD, i, 0);
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}
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writel(15, &chan->msch->ddrconf);
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move_to_access_state(chan);
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/* DDR3 and LPDDR3 are always 8 bank, no need detect */
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sdram_params->ch[channel].bk = 3;
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/* Detect Col and Row number*/
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ret = sdram_col_row_detect(dram, channel, sdram_params);
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if (ret)
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goto error;
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}
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/* Find NIU DDR configuration */
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ret = sdram_get_niu_config(sdram_params);
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if (ret)
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goto error;
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/* Find stride setting */
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ret = sdram_get_stride(sdram_params);
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if (ret)
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goto error;
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dram_all_config(dram, sdram_params);
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debug("%s done\n", __func__);
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return 0;
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error:
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printf("DRAM init failed!\n");
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hang();
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}
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#endif /* CONFIG_SPL_BUILD */
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@ -743,7 +946,6 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
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SYS_REG_BW_MASK));
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row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
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SYS_REG_ROW_3_4_MASK;
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chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
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if (rank > 1)
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@ -815,21 +1017,10 @@ static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
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struct rk3288_sdram_params *params = dev_get_platdata(dev);
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const void *blob = gd->fdt_blob;
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int node = dev->of_offset;
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int i, ret;
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int ret;
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params->num_channels = fdtdec_get_int(blob, node,
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"rockchip,num-channels", 1);
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for (i = 0; i < params->num_channels; i++) {
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ret = fdtdec_get_byte_array(blob, node,
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"rockchip,sdram-channel",
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(u8 *)¶ms->ch[i],
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sizeof(params->ch[i]));
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if (ret) {
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debug("%s: Cannot read rockchip,sdram-channel\n",
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__func__);
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return -EINVAL;
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}
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}
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/* Rk3288 supports dual-channel, set default channel num to 2 */
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params->num_channels = 2;
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ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
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(u32 *)¶ms->pctl_timing,
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sizeof(params->pctl_timing) / sizeof(u32));
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@ -870,18 +1061,15 @@ static int conv_of_platdata(struct udevice *dev)
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{
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struct rk3288_sdram_params *plat = dev_get_platdata(dev);
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struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
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int i, ret;
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int ret;
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for (i = 0; i < 2; i++) {
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memcpy(&plat->ch[i], of_plat->rockchip_sdram_channel,
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sizeof(plat->ch[i]));
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}
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memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
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sizeof(plat->pctl_timing));
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memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
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sizeof(plat->phy_timing));
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memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
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plat->num_channels = of_plat->rockchip_num_channels;
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/* Rk3288 supports dual-channel, set default channel num to 2 */
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plat->num_channels = 2;
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ret = regmap_init_mem_platdata(dev, of_plat->reg,
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ARRAY_SIZE(of_plat->reg) / 2,
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&plat->map);
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