ARM: keystone2: Fix dev and arm speed detection

Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.

Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
2015-07-28 14:16:44 +05:30
committed by Tom Rini
parent c321a23624
commit 7b50e1599f
12 changed files with 116 additions and 164 deletions

View File

@@ -26,14 +26,30 @@ unsigned int external_clk[ext_clk_count] = {
[usb_clk] = 100000000,
};
static struct pll_init_data core_pll_config[] = {
CORE_PLL_800,
CORE_PLL_850,
CORE_PLL_1000,
CORE_PLL_1250,
CORE_PLL_1350,
CORE_PLL_1400,
CORE_PLL_1500,
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_800,
[SPD850] = CORE_PLL_850,
[SPD1000] = CORE_PLL_1000,
[SPD1250] = CORE_PLL_1250,
[SPD1350] = CORE_PLL_1350,
[SPD1400] = CORE_PLL_1400,
[SPD1500] = CORE_PLL_1500,
};
/* DEV and ARM speed definitions as specified in DEVSPEED register */
int speeds[DEVSPEED_NUMSPDS] = {
SPD850,
SPD1000,
SPD1250,
SPD1350,
SPD1400,
SPD1500,
SPD1400,
SPD1350,
SPD1250,
SPD1000,
SPD850,
SPD800,
};
s16 divn_val[16] = {

View File

@@ -29,10 +29,10 @@ unsigned int external_clk[ext_clk_count] = {
[rp1_clk] = 123456789
};
static struct pll_init_data core_pll_config[] = {
CORE_PLL_799,
CORE_PLL_999,
CORE_PLL_1200,
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_999,
[SPD1200] = CORE_PLL_1200,
};
s16 divn_val[16] = {
@@ -40,11 +40,11 @@ s16 divn_val[16] = {
};
static struct pll_init_data tetris_pll_config[] = {
TETRIS_PLL_800,
TETRIS_PLL_1000,
TETRIS_PLL_1200,
TETRIS_PLL_1350,
TETRIS_PLL_1400,
[SPD800] = TETRIS_PLL_800,
[SPD1000] = TETRIS_PLL_1000,
[SPD1200] = TETRIS_PLL_1200,
[SPD1350] = TETRIS_PLL_1350,
[SPD1400] = TETRIS_PLL_1400,
};
static struct pll_init_data pa_pll_config =

View File

@@ -25,10 +25,10 @@ unsigned int external_clk[ext_clk_count] = {
[usb_clk] = 100000000,
};
static struct pll_init_data core_pll_config[] = {
CORE_PLL_799,
CORE_PLL_1000,
CORE_PLL_1198,
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_1000,
[SPD800] = CORE_PLL_1198,
};
s16 divn_val[16] = {
@@ -36,11 +36,11 @@ s16 divn_val[16] = {
};
static struct pll_init_data tetris_pll_config[] = {
TETRIS_PLL_799,
TETRIS_PLL_1000,
TETRIS_PLL_1198,
TETRIS_PLL_1352,
TETRIS_PLL_1401,
[SPD800] = TETRIS_PLL_799,
[SPD1000] = TETRIS_PLL_1000,
[SPD1200] = TETRIS_PLL_1198,
[SPD1350] = TETRIS_PLL_1352,
[SPD1400] = TETRIS_PLL_1401,
};
static struct pll_init_data pa_pll_config =