clk: imx: Add initial support for i.MXRT1170 clock driver
Add clock driver support for i.MXRT1170. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
This commit is contained in:
Jesse Taube
Stefano Babic
parent
2242ac5d80
commit
79f7632e80
@ -124,3 +124,19 @@ config CLK_IMXRT1050
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select CLK_COMPOSITE_CCF
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help
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This enables support clock driver for i.MXRT1050 platforms.
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config SPL_CLK_IMXRT1170
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bool "SPL clock support for i.MXRT1170"
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depends on ARCH_IMXRT && SPL
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select SPL_CLK
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select SPL_CLK_CCF
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help
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This enables SPL DM/DTS support for clock driver in i.MXRT1170.
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config CLK_IMXRT1170
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bool "Clock support for i.MXRT1170"
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depends on ARCH_IMXRT
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select CLK
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select CLK_CCF
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help
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This enables support clock driver for i.MXRT1170 platforms.
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@ -21,3 +21,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
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obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o
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221
drivers/clk/imx/clk-imxrt1170.c
Normal file
221
drivers/clk/imx/clk-imxrt1170.c
Normal file
@ -0,0 +1,221 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022
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* Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <dt-bindings/clock/imxrt1170-clock.h>
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#include "clk.h"
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static ulong imxrt1170_clk_get_rate(struct clk *clk)
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{
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struct clk *c;
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int ret;
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debug("%s(#%lu)\n", __func__, clk->id);
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ret = clk_get_by_id(clk->id, &c);
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if (ret)
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return ret;
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return clk_get_rate(c);
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}
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static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct clk *c;
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int ret;
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debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
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ret = clk_get_by_id(clk->id, &c);
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if (ret)
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return ret;
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return clk_set_rate(c, rate);
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}
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static int __imxrt1170_clk_enable(struct clk *clk, bool enable)
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{
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struct clk *c;
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int ret;
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debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
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ret = clk_get_by_id(clk->id, &c);
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if (ret)
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return ret;
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if (enable)
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ret = clk_enable(c);
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else
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ret = clk_disable(c);
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return ret;
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}
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static int imxrt1170_clk_disable(struct clk *clk)
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{
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return __imxrt1170_clk_enable(clk, 0);
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}
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static int imxrt1170_clk_enable(struct clk *clk)
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{
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return __imxrt1170_clk_enable(clk, 1);
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}
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static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk *c, *cp;
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int ret;
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debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
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ret = clk_get_by_id(clk->id, &c);
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if (ret)
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return ret;
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ret = clk_get_by_id(parent->id, &cp);
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if (ret)
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return ret;
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return clk_set_parent(c, cp);
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}
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static struct clk_ops imxrt1170_clk_ops = {
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.set_rate = imxrt1170_clk_set_rate,
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.get_rate = imxrt1170_clk_get_rate,
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.enable = imxrt1170_clk_enable,
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.disable = imxrt1170_clk_disable,
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.set_parent = imxrt1170_clk_set_parent,
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};
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static const char * const lpuart1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
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"pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3"};
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static const char * const gpt1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
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"pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3"};
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static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
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"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
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static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
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"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
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static int imxrt1170_clk_probe(struct udevice *dev)
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{
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void *base;
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/* Anatop clocks */
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base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
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clk_dm(IMXRT1170_CLK_RCOSC_48M,
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imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1));
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clk_dm(IMXRT1170_CLK_RCOSC_400M,
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imx_clk_fixed_factor("rcosc400M", "rcosc16M", 25, 1));
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clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2,
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imx_clk_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2));
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clk_dm(IMXRT1170_CLK_PLL_ARM,
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imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm", "osc",
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base + 0x200, 0xff));
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clk_dm(IMXRT1170_CLK_PLL3,
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imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll3_sys", "osc",
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base + 0x210, 1));
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clk_dm(IMXRT1170_CLK_PLL2,
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imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll2_sys", "osc",
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base + 0x240, 1));
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clk_dm(IMXRT1170_CLK_PLL3_PFD0,
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imx_clk_pfd("pll3_pfd0", "pll3_sys", base + 0x230, 0));
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clk_dm(IMXRT1170_CLK_PLL3_PFD1,
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imx_clk_pfd("pll3_pfd1", "pll3_sys", base + 0x230, 1));
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clk_dm(IMXRT1170_CLK_PLL3_PFD2,
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imx_clk_pfd("pll3_pfd2", "pll3_sys", base + 0x230, 2));
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clk_dm(IMXRT1170_CLK_PLL3_PFD3,
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imx_clk_pfd("pll3_pfd3", "pll3_sys", base + 0x230, 3));
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clk_dm(IMXRT1170_CLK_PLL2_PFD0,
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imx_clk_pfd("pll2_pfd0", "pll2_sys", base + 0x270, 0));
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clk_dm(IMXRT1170_CLK_PLL2_PFD1,
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imx_clk_pfd("pll2_pfd1", "pll2_sys", base + 0x270, 1));
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clk_dm(IMXRT1170_CLK_PLL2_PFD2,
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imx_clk_pfd("pll2_pfd2", "pll2_sys", base + 0x270, 2));
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clk_dm(IMXRT1170_CLK_PLL2_PFD3,
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imx_clk_pfd("pll2_pfd3", "pll2_sys", base + 0x270, 3));
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clk_dm(IMXRT1170_CLK_PLL3_DIV2,
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imx_clk_fixed_factor("pll3_div2", "pll3_sys", 1, 2));
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/* CCM clocks */
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base = dev_read_addr_ptr(dev);
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if (base == (void *)FDT_ADDR_T_NONE)
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return -EINVAL;
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clk_dm(IMXRT1170_CLK_LPUART1_SEL,
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imx_clk_mux("lpuart1_sel", base + (25 * 0x80), 8, 3,
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lpuart1_sels, ARRAY_SIZE(lpuart1_sels)));
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clk_dm(IMXRT1170_CLK_LPUART1,
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imx_clk_divider("lpuart1", "lpuart1_sel",
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base + (25 * 0x80), 0, 8));
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clk_dm(IMXRT1170_CLK_USDHC1_SEL,
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imx_clk_mux("usdhc1_sel", base + (58 * 0x80), 8, 3,
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usdhc1_sels, ARRAY_SIZE(usdhc1_sels)));
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clk_dm(IMXRT1170_CLK_USDHC1,
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imx_clk_divider("usdhc1", "usdhc1_sel",
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base + (58 * 0x80), 0, 8));
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clk_dm(IMXRT1170_CLK_GPT1_SEL,
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imx_clk_mux("gpt1_sel", base + (14 * 0x80), 8, 3,
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gpt1_sels, ARRAY_SIZE(gpt1_sels)));
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clk_dm(IMXRT1170_CLK_GPT1,
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imx_clk_divider("gpt1", "gpt1_sel",
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base + (14 * 0x80), 0, 8));
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clk_dm(IMXRT1170_CLK_SEMC_SEL,
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imx_clk_mux("semc_sel", base + (4 * 0x80), 8, 3,
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semc_sels, ARRAY_SIZE(semc_sels)));
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clk_dm(IMXRT1170_CLK_SEMC,
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imx_clk_divider("semc", "semc_sel",
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base + (4 * 0x80), 0, 8));
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struct clk *clk, *clk1;
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clk_get_by_id(IMXRT1170_CLK_PLL2_PFD2, &clk);
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clk_get_by_id(IMXRT1170_CLK_SEMC_SEL, &clk1);
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clk_enable(clk1);
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clk_set_parent(clk1, clk);
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clk_get_by_id(IMXRT1170_CLK_SEMC, &clk);
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clk_enable(clk);
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clk_set_rate(clk, 132000000UL);
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clk_get_by_id(IMXRT1170_CLK_GPT1, &clk);
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clk_enable(clk);
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clk_set_rate(clk, 32000000UL);
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return 0;
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}
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static const struct udevice_id imxrt1170_clk_ids[] = {
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{ .compatible = "fsl,imxrt1170-ccm" },
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{ },
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};
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U_BOOT_DRIVER(imxrt1170_clk) = {
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.name = "clk_imxrt1170",
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.id = UCLASS_CLK,
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.of_match = imxrt1170_clk_ids,
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.ops = &imxrt1170_clk_ops,
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.probe = imxrt1170_clk_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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