leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge tag 'rockchip-for-v2019.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
- rk3399 lpddr4 support
- rk3399-rock960 board support improvement
- Eliminate pyelftools dependency by make_fit_atf.py
- clean up rockchip dts to use -u-boot.dtsi
- use ARM arch/generic timer instead of rk_timer
- clean up Kconfig options for board support
This commit is contained in:
Tom Rini 2019-07-21 15:40:21 -04:00
commit 79ea03b38a
125 changed files with 8245 additions and 1391 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
arch/arm/dts/rk3288-evb-u-boot.dtsi Normal file
View File

@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
#include "rk3288-u-boot.dtsi"
&pinctrl {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};
&sdmmc_bus4 {
u-boot,dm-spl;
};
&sdmmc_clk {
u-boot,dm-spl;
};
&sdmmc_cmd {
u-boot,dm-spl;
};
&sdmmc_pwr {
u-boot,dm-spl;
};

25
arch/arm/dts/rk3288-evb.dts
View File

@ -26,31 +26,6 @@
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pwm1 {
status = "okay";
};
&uart2 {
u-boot,dm-pre-reloc;
reg-shift = <2>;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};

54
arch/arm/dts/rk3288-fennec-u-boot.dtsi Normal file
View File

@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
#include "rk3288-u-boot.dtsi"
&pinctrl {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};
&pcfg_pull_none_drv_8ma {
u-boot,dm-spl;
};
&pcfg_pull_up_drv_8ma {
u-boot,dm-spl;
};
&sdmmc_bus4 {
u-boot,dm-spl;
};
&sdmmc_clk {
u-boot,dm-spl;
};
&sdmmc_cmd {
u-boot,dm-spl;
};
&sdmmc_pwr {
u-boot,dm-spl;
};

25
arch/arm/dts/rk3288-fennec.dts
View File

@ -26,31 +26,6 @@
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pwm1 {
status = "okay";
};
&uart2 {
u-boot,dm-pre-reloc;
reg-shift = <2>;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};

50
arch/arm/dts/rk3288-firefly-u-boot.dtsi Normal file
View File

@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
#include "rk3288-u-boot.dtsi"
&pinctrl {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};
&pcfg_pull_up_drv_12ma {
u-boot,dm-spl;
};
&sdmmc_bus4 {
u-boot,dm-spl;
};
&sdmmc_clk {
u-boot,dm-spl;
};
&sdmmc_cmd {
u-boot,dm-spl;
};
&sdmmc_pwr {
u-boot,dm-spl;
};

23
arch/arm/dts/rk3288-firefly.dts
View File

@ -37,7 +37,6 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
act8846 {
pmic_vsel: pmic-vsel {
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
@ -59,25 +58,3 @@
&pwm1 {
status = "okay";
};
&uart2 {
u-boot,dm-pre-reloc;
reg-shift = <2>;
};
&usb_host1 {
vbus-supply = <&vcc_host_5v>;
status = "okay";
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};

26
arch/arm/dts/rk3288-firefly.dtsi
View File

@ -320,6 +320,11 @@
output-low;
};
pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
bias-pull-up;
drive-strength = <12>;
};
act8846 {
pwr_hold: pwr-hold {
rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
@ -363,8 +368,27 @@
};
sdmmc {
/*
* Default drive strength isn't enough to achieve even
* high-speed mode on firefly board so bump up to 12ma.
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
<6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
<6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
<6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
};
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

38
arch/arm/dts/rk3288-miqi-u-boot.dtsi Normal file
View File

@ -0,0 +1,38 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
#include "rk3288-u-boot.dtsi"
&pinctrl {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&sdmmc_bus4 {
u-boot,dm-spl;
};
&sdmmc_clk {
u-boot,dm-spl;
};
&sdmmc_cmd {
u-boot,dm-spl;
};
&sdmmc_pwr {
u-boot,dm-spl;
};

18
arch/arm/dts/rk3288-miqi.dts
View File

@ -25,21 +25,3 @@
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
reg-shift = <2>;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};

46
arch/arm/dts/rk3288-popmetal-u-boot.dtsi Normal file
View File

@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
#include "rk3288-u-boot.dtsi"
&pinctrl {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};
&sdmmc_bus4 {
u-boot,dm-spl;
};
&sdmmc_clk {
u-boot,dm-spl;
};
&sdmmc_cmd {
u-boot,dm-spl;
};
&sdmmc_pwr {
u-boot,dm-spl;
};

26
arch/arm/dts/rk3288-popmetal.dts
View File

@ -26,32 +26,6 @@
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pwm1 {
status = "okay";
};
&uart2 {
u-boot,dm-pre-reloc;
reg-shift = <2>;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};

7
arch/arm/dts/rk3288-u-boot.dtsi
View File

@ -3,6 +3,13 @@
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
/ {
chosen {
u-boot,spl-boot-order = \
"same-as-spl", &emmc, &sdmmc;
};
};
&dmc {
u-boot,dm-pre-reloc;
};

1
arch/arm/dts/rk3368-lion-u-boot.dtsi
View File

@ -12,7 +12,6 @@
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = &emmc, &sdmmc;
tick-timer = "/timer@ff810000";
};
};

1
arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
View File

@ -5,7 +5,6 @@
/ {
chosen {
u-boot,spl-boot-order = &emmc;
tick-timer = "/timer@ff810000";
};
};

92
arch/arm/dts/rk3399-ficus.dts
View File

@ -23,6 +23,52 @@
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>,
<&user_led4>, <&wlan_led>, <&bt_led>;
user_led1 {
label = "red:user1";
gpios = <&gpio4 25 0>;
linux,default-trigger = "heartbeat";
};
user_led2 {
label = "red:user2";
gpios = <&gpio4 26 0>;
linux,default-trigger = "mmc0";
};
user_led3 {
label = "red:user3";
gpios = <&gpio4 30 0>;
linux,default-trigger = "mmc1";
};
user_led4 {
label = "red:user4";
gpios = <&gpio1 0 0>;
panic-indicator;
linux,default-trigger = "none";
};
wlan_active_led {
label = "red:wlan";
gpios = <&gpio1 1 0>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
bt_active_led {
label = "red:bt";
gpios = <&gpio1 4 0>;
linux,default-trigger = "hci0-power";
default-state = "off";
};
};
};
&gmac {
@ -49,23 +95,63 @@
gmac {
rgmii_sleep_pins: rgmii-sleep-pins {
rockchip,pins =
<3 15 RK_FUNC_GPIO &pcfg_output_low>;
<3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
};
};
pcie {
pcie_drv: pcie-drv {
rockchip,pins =
<1 24 RK_FUNC_GPIO &pcfg_pull_none>;
<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb2 {
host_vbus_drv: host-vbus-drv {
rockchip,pins =
<4 27 RK_FUNC_GPIO &pcfg_pull_none>;
<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
user_led1: user_led1 {
rockchip,pins =
<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led2: user_led2 {
rockchip,pins =
<4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led3: user_led3 {
rockchip,pins =
<4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led4: user_led4 {
rockchip,pins =
<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
wlan_led: wlan_led {
rockchip,pins =
<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_led: bt_led {
rockchip,pins =
<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&usbdrd_dwc3_0 {
dr_mode = "host";
};
&usbdrd_dwc3_1 {
dr_mode = "host";
};
&vcc3v3_pcie {

1
arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
View File

@ -4,3 +4,4 @@
*/
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1866.dtsi"

7
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
View File

@ -4,3 +4,10 @@
*/
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};

91
arch/arm/dts/rk3399-rock960.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (c) 2018 Linaro Ltd.
*/
/dts-v1/;
@ -13,6 +13,53 @@
chosen {
stdout-path = "serial2:1500000n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>,
<&user_led4>, <&wlan_led>, <&bt_led>;
user_led1 {
label = "green:user1";
gpios = <&gpio4 RK_PC2 0>;
linux,default-trigger = "heartbeat";
};
user_led2 {
label = "green:user2";
gpios = <&gpio4 RK_PC6 0>;
linux,default-trigger = "mmc0";
};
user_led3 {
label = "green:user3";
gpios = <&gpio4 RK_PD0 0>;
linux,default-trigger = "mmc1";
};
user_led4 {
label = "green:user4";
gpios = <&gpio4 RK_PD4 0>;
panic-indicator;
linux,default-trigger = "none";
};
wlan_active_led {
label = "yellow:wlan";
gpios = <&gpio4 RK_PD5 0>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
bt_active_led {
label = "blue:bt";
gpios = <&gpio4 RK_PD6 0>;
linux,default-trigger = "hci0-power";
default-state = "off";
};
};
};
&pcie0 {
@ -20,6 +67,38 @@
};
&pinctrl {
leds {
user_led1: user_led1 {
rockchip,pins =
<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led2: user_led2 {
rockchip,pins =
<4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led3: user_led3 {
rockchip,pins =
<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led4: user_led4 {
rockchip,pins =
<4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
wlan_led: wlan_led {
rockchip,pins =
<4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_led: bt_led {
rockchip,pins =
<4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_drv: pcie-drv {
rockchip,pins =
@ -35,6 +114,14 @@
};
};
&usbdrd_dwc3_0 {
dr_mode = "otg";
};
&usbdrd_dwc3_1 {
dr_mode = "host";
};
&vcc3v3_pcie {
gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
};

233
arch/arm/dts/rk3399-rock960.dtsi
View File

@ -1,13 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
* Copyright (c) 2018 Linaro Ltd.
*/
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vcc1v8_s0: vcc1v8-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s0";
@ -16,12 +35,13 @@
regulator-always-on;
};
vcc_sys: vcc-sys {
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-name = "vcc5v0_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&vcc12v_dcin>;
};
vcc3v3_sys: vcc3v3-sys {
@ -30,7 +50,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
@ -54,20 +74,8 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
vin-supply = <&vcc5v0_sys>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 0>;
regulator-name = "vdd_log";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
};
&cpu_l0 {
@ -98,7 +106,19 @@
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
@ -118,7 +138,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
vin-supply = <&vcc5v0_sys>;
status = "okay";
regulator-state-mem {
@ -136,7 +156,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
@ -154,16 +174,16 @@
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
@ -344,6 +364,10 @@
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
@ -370,45 +394,92 @@
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins =
<4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
<4 RK_PB0 1 &pcfg_pull_up_8ma>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
<4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
<4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
<4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
<4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
<4 RK_PB0 1 &pcfg_pull_up_8ma>,
<4 RK_PB1 1 &pcfg_pull_up_8ma>,
<4 RK_PB2 1 &pcfg_pull_up_8ma>,
<4 RK_PB3 1 &pcfg_pull_up_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
<4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
<4 RK_PB4 1 &pcfg_pull_none_18ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
<4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
<4 RK_PB5 1 &pcfg_pull_up_8ma>;
};
};
sdio0 {
sdio0_bus4: sdio0-bus4 {
rockchip,pins =
<2 RK_PC4 1 &pcfg_pull_up_20ma>,
<2 RK_PC5 1 &pcfg_pull_up_20ma>,
<2 RK_PC6 1 &pcfg_pull_up_20ma>,
<2 RK_PC7 1 &pcfg_pull_up_20ma>;
};
sdio0_cmd: sdio0-cmd {
rockchip,pins =
<2 RK_PD0 1 &pcfg_pull_up_20ma>;
};
sdio0_clk: sdio0-clk {
rockchip,pins =
<2 RK_PD1 1 &pcfg_pull_none_20ma>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
rockchip,pins =
<1 17 RK_FUNC_GPIO &pcfg_pull_down>;
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins =
<1 14 RK_FUNC_GPIO &pcfg_pull_down>;
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins =
<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
@ -421,6 +492,32 @@
status = "okay";
};
&sdio0 {
bus-width = <4>;
clock-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
@ -445,16 +542,42 @@
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
rockchip,hw-tshut-temp = <110000>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
};
};
&uart2 {
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&u2phy0 {
status = "okay";
};
@ -497,10 +620,34 @@
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

1
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
View File

@ -4,6 +4,7 @@
*/
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
&vdd_log {
regulator-init-microvolt = <950000>;

1537
arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/dts/rk3399-u-boot.dtsi
View File

@ -3,6 +3,10 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
&pmu {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};

72
arch/arm/include/asm/arch-rockchip/pmu_rk3399.h Normal file
View File

@ -0,0 +1,72 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
*
*/
#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__
#define __SOC_ROCKCHIP_RK3399_PMU_H__
struct rk3399_pmu_regs {
u32 pmu_wakeup_cfg[5];
u32 pmu_pwrdn_con;
u32 pmu_pwrdn_st;
u32 pmu_pll_con;
u32 pmu_pwrmode_con;
u32 pmu_sft_con;
u32 pmu_int_con;
u32 pmu_int_st;
u32 pmu_gpio0_pos_int_con;
u32 pmu_gpio0_net_int_con;
u32 pmu_gpio1_pos_int_con;
u32 pmu_gpio1_net_int_con;
u32 pmu_gpio0_pos_int_st;
u32 pmu_gpio0_net_int_st;
u32 pmu_gpio1_pos_int_st;
u32 pmu_gpio1_net_int_st;
u32 pmu_pwrdn_inten;
u32 pmu_pwrdn_status;
u32 pmu_wakeup_status;
u32 pmu_bus_clr;
u32 pmu_bus_idle_req;
u32 pmu_bus_idle_st;
u32 pmu_bus_idle_ack;
u32 pmu_cci500_con;
u32 pmu_adb400_con;
u32 pmu_adb400_st;
u32 pmu_power_st;
u32 pmu_core_pwr_st;
u32 pmu_osc_cnt;
u32 pmu_plllock_cnt;
u32 pmu_pllrst_cnt;
u32 pmu_stable_cnt;
u32 pmu_ddrio_pwron_cnt;
u32 pmu_wakeup_rst_clr_cnt;
u32 pmu_ddr_sref_st;
u32 pmu_scu_l_pwrdn_cnt;
u32 pmu_scu_l_pwrup_cnt;
u32 pmu_scu_b_pwrdn_cnt;
u32 pmu_scu_b_pwrup_cnt;
u32 pmu_gpu_pwrdn_cnt;
u32 pmu_gpu_pwrup_cnt;
u32 pmu_center_pwrdn_cnt;
u32 pmu_center_pwrup_cnt;
u32 pmu_timeout_cnt;
u32 pmu_cpu0apm_con;
u32 pmu_cpu1apm_con;
u32 pmu_cpu2apm_con;
u32 pmu_cpu3apm_con;
u32 pmu_cpu0bpm_con;
u32 pmu_cpu1bpm_con;
u32 pmu_noc_auto_ena;
u32 pmu_pwrdn_con1;
u32 reserved0[0x4];
u32 pmu_sys_reg_reg0;
u32 pmu_sys_reg_reg1;
u32 pmu_sys_reg_reg2;
u32 pmu_sys_reg_reg3;
};
check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */

6
arch/arm/include/asm/arch-rockchip/sdram.h
View File

@ -8,12 +8,6 @@
#ifndef _ASM_ARCH_RK3288_SDRAM_H__
#define _ASM_ARCH_RK3288_SDRAM_H__
enum {
DDR3 = 3,
LPDDR3 = 6,
UNUSED = 0xFF,
};
struct rk3288_sdram_channel {
/*
* bit width in address, eg:

90
arch/arm/include/asm/arch-rockchip/sdram_common.h
View File

@ -5,6 +5,44 @@
#ifndef _ASM_ARCH_SDRAM_COMMON_H
#define _ASM_ARCH_SDRAM_COMMON_H
enum {
DDR4 = 0,
DDR3 = 0x3,
LPDDR2 = 0x5,
LPDDR3 = 0x6,
LPDDR4 = 0x7,
UNUSED = 0xFF
};
struct sdram_cap_info {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
unsigned int col;
/* dram bank number, 3:8bank, 2:4bank */
unsigned int bk;
/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned int bw;
/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned int dbw;
/*
* row_3_4 = 1: 6Gb or 12Gb die
* row_3_4 = 0: normal die, power of 2
*/
unsigned int row_3_4;
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int ddrconfig;
};
struct sdram_base_params {
unsigned int ddr_freq;
unsigned int dramtype;
unsigned int num_channels;
unsigned int stride;
unsigned int odt;
};
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
@ -28,30 +66,82 @@
* [1:0] dbw_ch0
*/
#define SYS_REG_DDRTYPE_SHIFT 13
#define DDR_SYS_REG_VERSION 2
#define SYS_REG_DDRTYPE_MASK 7
#define SYS_REG_NUM_CH_SHIFT 12
#define SYS_REG_NUM_CH_MASK 1
#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
#define SYS_REG_ROW_3_4_MASK 1
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT)
#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \
SYS_REG_NUM_CH_SHIFT)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
SYS_REG_RANK_SHIFT(ch))
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
#define SYS_REG_COL_MASK 3
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
#define SYS_REG_BK_MASK 1
#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
SYS_REG_BK_SHIFT(ch))
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
#define SYS_REG_ENC_VERSION(n) ((n) << 28)
#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
(5 + 2 * (ch)); \
} while (0)
#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
(os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
(os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
(os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
(4 + 2 * (ch)); \
} while (0)
#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch))
#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
/* Called by U-Boot board_init_r for Rockchip SoCs */
int dram_init(void);
#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
inline void sdram_print_dram_type(unsigned char dramtype)
{
}
inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base)
{
}
inline void sdram_print_stride(unsigned int stride)
{
}
#else
void sdram_print_dram_type(unsigned char dramtype);
void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base);
void sdram_print_stride(unsigned int stride);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
#endif

7
arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
View File

@ -7,13 +7,6 @@
#include <common.h>
enum {
DDR3 = 3,
LPDDR2 = 5,
LPDDR3 = 6,
UNUSED = 0xFF,
};
struct rk322x_sdram_channel {
/*
* bit width in address, eg:

65
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
View File

@ -6,14 +6,6 @@
#ifndef _ASM_ARCH_SDRAM_RK3399_H
#define _ASM_ARCH_SDRAM_RK3399_H
enum {
DDR3 = 0x3,
LPDDR2 = 0x5,
LPDDR3 = 0x6,
LPDDR4 = 0x7,
UNUSED = 0xFF
};
struct rk3399_ddr_pctl_regs {
u32 denali_ctl[332];
};
@ -26,6 +18,31 @@ struct rk3399_ddr_pi_regs {
u32 denali_pi[200];
};
union noc_ddrtimingc0 {
u32 d32;
struct {
unsigned burstpenalty : 4;
unsigned reserved0 : 4;
unsigned wrtomwr : 6;
unsigned reserved1 : 18;
} b;
};
union noc_ddrmode {
u32 d32;
struct {
unsigned autoprecharge : 1;
unsigned bypassfiltering : 1;
unsigned fawbank : 1;
unsigned burstsize : 2;
unsigned mwrsize : 2;
unsigned reserved2 : 1;
unsigned forceorder : 8;
unsigned forceorderstate : 8;
unsigned reserved3 : 8;
} b;
};
struct rk3399_msch_regs {
u32 coreid;
u32 revisionid;
@ -44,9 +61,9 @@ struct rk3399_msch_regs {
struct rk3399_msch_timings {
u32 ddrtiminga0;
u32 ddrtimingb0;
u32 ddrtimingc0;
union noc_ddrtimingc0 ddrtimingc0;
u32 devtodev0;
u32 ddrmode;
union noc_ddrmode ddrmode;
u32 agingx0;
};
@ -72,37 +89,13 @@ struct rk3399_ddr_cic_regs {
#define MEM_RST_VALID 1
struct rk3399_sdram_channel {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
unsigned int col;
/* dram bank number, 3:8bank, 2:4bank */
unsigned int bk;
/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned int bw;
/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned int dbw;
/*
* row_3_4 = 1: 6Gb or 12Gb die
* row_3_4 = 0: normal die, power of 2
*/
unsigned int row_3_4;
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int ddrconfig;
struct sdram_cap_info cap_info;
struct rk3399_msch_timings noc_timings;
};
struct rk3399_base_params {
unsigned int ddr_freq;
unsigned int dramtype;
unsigned int num_channels;
unsigned int stride;
unsigned int odt;
};
struct rk3399_sdram_params {
struct rk3399_sdram_channel ch[2];
struct rk3399_base_params base;
struct sdram_base_params base;
struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs;

22
arch/arm/include/asm/arch-rockchip/sys_proto.h
View File

@ -6,28 +6,6 @@
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
#ifdef CONFIG_ROCKCHIP_RK3288
#include <asm/armv7.h>
static void configure_l2ctlr(void)
{
uint32_t l2ctlr;
l2ctlr = read_l2ctlr();
l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
/*
* Data RAM write latency: 2 cycles
* Data RAM read latency: 2 cycles
* Data RAM setup latency: 1 cycle
* Tag RAM write latency: 1 cycle
* Tag RAM read latency: 1 cycle
* Tag RAM setup latency: 1 cycle
*/
l2ctlr |= (1 << 3 | 1 << 0);
write_l2ctlr(l2ctlr);
}
#endif /* CONFIG_ROCKCHIP_RK3288 */
/* provided to defeat compiler optimisation in board_init_f() */
void gru_dummy_function(int i);

3
arch/arm/include/asm/arch-rockchip/timer.h
View File

@ -15,7 +15,4 @@ struct rk_timer {
u32 timer_int_status;
};
void rockchip_timer_init(void);
void rockchip_udelay(unsigned int usec);
#endif

78
arch/arm/mach-rockchip/Kconfig
View File

@ -59,6 +59,8 @@ config ROCKCHIP_RK322X
select SPL_DRIVERS_MISC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
imply TPL_BOOTROM_SUPPORT
imply TPL_ROCKCHIP_COMMON_BOARD
select ROCKCHIP_BROM_HELPER
select TPL_LIBCOMMON_SUPPORT
select TPL_LIBGENERIC_SUPPORT
@ -68,19 +70,6 @@ config ROCKCHIP_RK322X
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
if ROCKCHIP_RK322X
config TPL_TEXT_BASE
default 0x10081000
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0x10088000
endif
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7A
@ -100,6 +89,7 @@ config ROCKCHIP_RK3288
imply TPL_OF_PLATDATA
imply TPL_RAM
imply TPL_REGMAP
imply TPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL_SUPPORT
imply TPL_SYSCON
imply USB_FUNCTION_ROCKUSB
@ -111,19 +101,6 @@ config ROCKCHIP_RK3288
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
if ROCKCHIP_RK3288
config TPL_TEXT_BASE
default 0xff704000
config TPL_MAX_SIZE
default 32768
config TPL_STACK
default 0xff718000
endif
config ROCKCHIP_RK3328
bool "Support Rockchip RK3328"
select ARM64
@ -151,6 +128,7 @@ config ROCKCHIP_RK3368
imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
imply TPL_ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
into a big and little cluster with 4 cores each) Cortex-A53 including
@ -162,19 +140,6 @@ config ROCKCHIP_RK3368
On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
I2S, UARTs, SPI, I2C and PWMs.
if ROCKCHIP_RK3368
config TPL_TEXT_BASE
default 0xff8c1000
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0xff8cffff
endif
config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
select ARM64
@ -209,7 +174,6 @@ config ROCKCHIP_RK3399
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SYS_MALLOC_SIMPLE
imply TPL_BOARD_INIT
imply TPL_BOOTROM_SUPPORT
imply TPL_DRIVERS_MISC_SUPPORT
imply TPL_OF_CONTROL
@ -219,6 +183,7 @@ config ROCKCHIP_RK3399
imply TPL_RAM
imply TPL_CLK
imply TPL_TINY_MEMSET
imply TPL_ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
@ -227,22 +192,6 @@ config ROCKCHIP_RK3399
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
if ROCKCHIP_RK3399
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_TEXT_BASE
default 0xff8c2000
config TPL_MAX_SIZE
default 188416
config TPL_STACK
default 0xff8effff
endif
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
@ -278,16 +227,17 @@ config TPL_ROCKCHIP_BACK_TO_BROM
SPL will return to the boot rom, which will then load the U-Boot
binary to keep going on.
config TPL_ROCKCHIP_COMMON_BOARD
bool ""
depends on TPL
help
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
common board is a basic TPL board init which can be shared for most
of SoCs to avoid copy-pase for different SoCs.
config ROCKCHIP_BOOT_MODE_REG
hex "Rockchip boot mode flag register address"
default 0x200081c8 if ROCKCHIP_RK3036
default 0x20004040 if ROCKCHIP_RK3188
default 0x110005c8 if ROCKCHIP_RK322X
default 0xff730094 if ROCKCHIP_RK3288
default 0xff738200 if ROCKCHIP_RK3368
default 0xff320300 if ROCKCHIP_RK3399
default 0x10300580 if ROCKCHIP_RV1108
default 0
help
The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
according to the value from this register.

14
arch/arm/mach-rockchip/Makefile
View File

@ -8,16 +8,12 @@
# the stack-pointer is valid before switching to the U-Boot stack).
obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o
obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o
obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o spl-boot-order.o
obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
@ -41,12 +37,6 @@ endif
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
ifndef CONFIG_ARM64
ifndef CONFIG_ROCKCHIP_RK3188
obj-y += rk_timer.o
endif
endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
ifndef CONFIG_TPL_BUILD

73
arch/arm/mach-rockchip/make_fit_atf.py
View File

@ -13,16 +13,7 @@ import os
import sys
import getopt
import logging
# pip install pyelftools
from elftools.elf.elffile import ELFFile
ELF_SEG_P_TYPE = 'p_type'
ELF_SEG_P_PADDR = 'p_paddr'
ELF_SEG_P_VADDR = 'p_vaddr'
ELF_SEG_P_OFFSET = 'p_offset'
ELF_SEG_P_FILESZ = 'p_filesz'
ELF_SEG_P_MEMSZ = 'p_memsz'
import struct
DT_HEADER = """
/*
@ -118,33 +109,19 @@ def append_conf_node(file, dtbs, segments):
file.write('\n')
def generate_atf_fit_dts_uboot(fit_file, uboot_file_name):
num_load_seg = 0
p_paddr = 0xFFFFFFFF
with open(uboot_file_name, 'rb') as uboot_file:
uboot = ELFFile(uboot_file)
for i in range(uboot.num_segments()):
seg = uboot.get_segment(i)
if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
num_load_seg = num_load_seg + 1
assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1)
segments = unpack_elf(uboot_file_name)
if len(segments) != 1:
raise ValueError("Invalid u-boot ELF image '%s'" % uboot_file_name)
index, entry, p_paddr, data = segments[0]
fit_file.write(DT_UBOOT % p_paddr)
def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name):
with open(bl31_file_name, 'rb') as bl31_file:
bl31 = ELFFile(bl31_file)
elf_entry = bl31.header['e_entry']
segments = bl31.num_segments()
for i in range(segments):
seg = bl31.get_segment(i)
if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
paddr = seg.__getitem__(ELF_SEG_P_PADDR)
append_bl31_node(fit_file, i + 1, paddr, elf_entry)
segments = unpack_elf(bl31_file_name)
for index, entry, paddr, data in segments:
append_bl31_node(fit_file, index + 1, paddr, entry)
append_fdt_node(fit_file, dtbs_file_name)
fit_file.write(DT_IMAGES_NODE_END)
append_conf_node(fit_file, dtbs_file_name, segments)
append_conf_node(fit_file, dtbs_file_name, len(segments))
def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
# Generate FIT script for ATF image.
@ -162,17 +139,29 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_fi
fit_file.close()
def generate_atf_binary(bl31_file_name):
with open(bl31_file_name, 'rb') as bl31_file:
bl31 = ELFFile(bl31_file)
for index, entry, paddr, data in unpack_elf(bl31_file_name):
file_name = 'bl31_0x%08x.bin' % paddr
with open(file_name, "wb") as atf:
atf.write(data)
num = bl31.num_segments()
for i in range(num):
seg = bl31.get_segment(i)
if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
paddr = seg.__getitem__(ELF_SEG_P_PADDR)
file_name = 'bl31_0x%08x.bin' % paddr
with open(file_name, "wb") as atf:
atf.write(seg.data())
def unpack_elf(filename):
with open(filename, 'rb') as file:
elf = file.read()
if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00':
raise ValueError("Invalid arm64 ELF file '%s'" % filename)
e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18)
e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36)
segments = []
for index in range(e_phnum):
offset = e_phoff + e_phentsize * index
p_type, p_flags, p_offset = struct.unpack_from('<LLQ', elf, offset)
if p_type == 1: # PT_LOAD
p_paddr, p_filesz = struct.unpack_from('<2Q', elf, offset + 0x18)
p_data = elf[p_offset:p_offset + p_filesz]
segments.append((index, e_entry, p_paddr, p_data))
return segments
def main():
uboot_elf = "./u-boot"

29
arch/arm/mach-rockchip/rk3036-board-spl.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
* (C) Copyright 2015-2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
@ -8,14 +8,37 @@
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/sdram_rk3036.h>
#include <asm/arch-rockchip/timer.h>
#define TIMER_LOAD_COUNT_L 0x00
#define TIMER_LOAD_COUNT_H 0x04
#define TIMER_CONTROL_REG 0x10
#define TIMER_EN 0x1
#define TIMER_FMODE (0 << 1)
#define TIMER_RMODE (1 << 1)
void rockchip_stimer_init(void)
{
asm volatile("mcr p15, 0, %0, c14, c0, 0"
: : "r"(COUNTER_FREQUENCY));
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
TIMER_CONTROL_REG);
}
void board_init_f(ulong dummy)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
rockchip_timer_init();
/* Init secure timer */
rockchip_stimer_init();
/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
timer_init();
sdram_init();
/* return to maskrom */

1
arch/arm/mach-rockchip/rk3036-board.c
View File

@ -14,7 +14,6 @@
#include <asm/arch-rockchip/grf_rk3036.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <asm/arch-rockchip/sdram_rk3036.h>
#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;

8
arch/arm/mach-rockchip/rk3036/Kconfig
View File

@ -1,5 +1,8 @@
if ROCKCHIP_RK3036
choice
prompt "RK3036 board select"
config TARGET_EVB_RK3036
bool "EVB_RK3036"
select BOARD_LATE_INIT
@ -8,6 +11,11 @@ config TARGET_KYLIN_RK3036
bool "KYLIN_RK3036"
select BOARD_LATE_INIT
endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0x200081c8
config SYS_SOC
default "rk3036"

19
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
View File

@ -9,7 +9,6 @@
#include <asm/arch-rockchip/grf_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/sdram_rk3036.h>
#include <asm/arch-rockchip/timer.h>
#include <asm/arch-rockchip/uart.h>
/*
@ -345,7 +344,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
/* waiting for pll lock */
while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
rockchip_udelay(1);
udelay(1);
/* PLL enter normal-mode */
rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
@ -373,25 +372,25 @@ void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
rockchip_udelay(10);
udelay(10);
rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
1 << DDRPHY_SRST_SHIFT);
rockchip_udelay(10);
udelay(10);
rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
1 << DDRCTRL_SRST_SHIFT);
rockchip_udelay(10);
udelay(10);
clrsetbits_le32(&ddr_phy->ddrphy_reg1,
SOFT_RESET_MASK << SOFT_RESET_SHIFT,
0 << SOFT_RESET_SHIFT);
rockchip_udelay(10);
udelay(10);
clrsetbits_le32(&ddr_phy->ddrphy_reg1,
SOFT_RESET_MASK << SOFT_RESET_SHIFT,
3 << SOFT_RESET_SHIFT);
rockchip_udelay(1);
udelay(1);
}
void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
@ -444,7 +443,7 @@ static void send_command(struct rk3036_ddr_pctl *pctl,
u32 rank, u32 cmd, u32 arg)
{
writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
rockchip_udelay(1);
udelay(1);
while (readl(&pctl->mcmd) & START_CMD)
;
}
@ -454,7 +453,7 @@ static void memory_init(struct rk3036_sdram_priv *priv)
struct rk3036_ddr_pctl *pctl = priv->pctl;
send_command(pctl, 3, DESELECT_CMD, 0);
rockchip_udelay(1);
udelay(1);
send_command(pctl, 3, PREA_CMD, 0);
send_command(pctl, 3, MRS_CMD,
(0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
@ -492,7 +491,7 @@ static void data_training(struct rk3036_sdram_priv *priv)
clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
rockchip_udelay(1);
udelay(1);
while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
(HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
;

3
arch/arm/mach-rockchip/rk3128-board.c
View File

@ -12,7 +12,6 @@
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/grf_rk3128.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <asm/arch-rockchip/timer.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
@ -33,8 +32,6 @@ int board_init(void)
{
int ret = 0;
rockchip_timer_init();
ret = regulators_enable_boot_on(false);
if (ret) {
debug("%s: Cannot enable boot on regulator\n", __func__);

3
arch/arm/mach-rockchip/rk3128/Kconfig
View File

@ -13,6 +13,9 @@ config TARGET_EVB_RK3128
endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0x100a0038
config SYS_SOC
default "rk3128"

2
arch/arm/mach-rockchip/rk3188-board-spl.c
View File

@ -22,8 +22,6 @@
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/pmu_rk3188.h>
#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/timer.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <dm/test.h>
#include <dm/util.h>

31
arch/arm/mach-rockchip/rk3188-board.c
View File

@ -15,7 +15,6 @@
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <dm/pinctrl.h>
__weak int rk_board_late_init(void)
{
@ -42,37 +41,7 @@ int board_late_init(void)
int board_init(void)
{
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
struct udevice *pinctrl;
int ret;
/*
* We need to implement sdcard iomux here for the further
* initialization, otherwise, it'll hit sdcard command sending
* timeout exception.
*/
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
goto err;
}
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
if (ret) {
debug("%s: Failed to set up SD card\n", __func__);
goto err;
}
return 0;
err:
printf("board_init: Error %d\n", ret);
/* No way to report error here */
hang();
return -1;
#else
return 0;
#endif
}
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)

3
arch/arm/mach-rockchip/rk3188/Kconfig
View File

@ -9,6 +9,9 @@ config TARGET_ROCK
Expansion connectors provide access to display pins, I2C, SPI,
UART and GPIOs.
config ROCKCHIP_BOOT_MODE_REG
default 0x20004040
config SYS_SOC
default "rk3188"

30
arch/arm/mach-rockchip/rk322x-board-spl.c
View File

@ -19,6 +19,31 @@ u32 spl_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
}
#define TIMER_LOAD_COUNT_L 0x00
#define TIMER_LOAD_COUNT_H 0x04
#define TIMER_CONTROL_REG 0x10
#define TIMER_EN 0x1
#define TIMER_FMODE BIT(0)
#define TIMER_RMODE BIT(1)
void rockchip_stimer_init(void)
{
/* If Timer already enabled, don't re-init it */
u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
if (reg & TIMER_EN)
return;
asm volatile("mcr p15, 0, %0, c14, c0, 0"
: : "r"(COUNTER_FREQUENCY));
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
TIMER_CONTROL_REG);
}
#define SGRF_DDR_CON0 0x10150000
void board_init_f(ulong dummy)
{
@ -31,6 +56,11 @@ void board_init_f(ulong dummy)
}
preloader_console_init();
/* Init secure timer */
rockchip_stimer_init();
/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
timer_init();
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
}

53
arch/arm/mach-rockchip/rk322x-board-tpl.c
View File

@ -1,53 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/timer.h>
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("TPL Init");
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
rockchip_timer_init();
printf("timer init done\n");
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return;
}
#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}

21
arch/arm/mach-rockchip/rk322x/Kconfig
View File

@ -1,18 +1,37 @@
if ROCKCHIP_RK322X
config TARGET_EVB_RK3229
bool "EVB_RK3229"
select BOARD_LATE_INIT
config ROCKCHIP_BOOT_MODE_REG
default 0x110005c8
config SYS_SOC
default "rk322x"
config SYS_MALLOC_F_LEN
default 0x400
default 0x800
config SPL_LIBCOMMON_SUPPORT
default y
config SPL_LIBGENERIC_SUPPORT
default y
config SPL_SERIAL_SUPPORT
default y
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0x10088000
config TPL_TEXT_BASE
default 0x10081000
source "board/rockchip/evb_rk3229/Kconfig"
endif

40
arch/arm/mach-rockchip/rk3288-board-spl.c
View File

@ -22,8 +22,6 @@
#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sys_proto.h>
#include <asm/arch-rockchip/timer.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <dm/test.h>
#include <dm/util.h>
@ -104,6 +102,36 @@ static int phycore_init(void)
}
#endif
__weak int arch_cpu_init(void)
{
return 0;
}
#define TIMER_LOAD_COUNT_L 0x00
#define TIMER_LOAD_COUNT_H 0x04
#define TIMER_CONTROL_REG 0x10
#define TIMER_EN 0x1
#define TIMER_FMODE BIT(0)
#define TIMER_RMODE BIT(1)
void rockchip_stimer_init(void)
{
/* If Timer already enabled, don't re-init it */
u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
if (reg & TIMER_EN)
return;
asm volatile("mcr p15, 0, %0, c14, c0, 0"
: : "r"(COUNTER_FREQUENCY));
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
TIMER_CONTROL_REG);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
@ -127,8 +155,12 @@ void board_init_f(ulong dummy)
hang();
}
rockchip_timer_init();
configure_l2ctlr();
/* Init secure timer */
rockchip_stimer_init();
/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
timer_init();
arch_cpu_init();
ret = rockchip_get_clk(&dev);
if (ret) {

70
arch/arm/mach-rockchip/rk3288-board-tpl.c
View File

@ -1,70 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Amarula Solutions
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/sys_proto.h>
#include <asm/arch-rockchip/timer.h>
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
rockchip_timer_init();
configure_l2ctlr();
ret = rockchip_get_clk(&dev);
if (ret) {
debug("CLK init failed: %d\n", ret);
return;
}
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
return;
}
}
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_board_init(void)
{
puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
U_BOOT_TIME ")\n");
}

27
arch/arm/mach-rockchip/rk3288-board.c
View File

@ -16,7 +16,6 @@
#include <asm/arch-rockchip/qos_rk3288.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <power/regulator.h>
@ -145,33 +144,7 @@ static int veyron_init(void)
int board_init(void)
{
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
struct udevice *pinctrl;
int ret;
/*
* We need to implement sdcard iomux here for the further
* initlization, otherwise, it'll hit sdcard command sending
* timeout exception.
*/
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
goto err;
}
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
if (ret) {
debug("%s: Failed to set up SD card\n", __func__);
goto err;
}
return 0;
err:
printf("board_init: Error %d\n", ret);
/* No way to report error here */
hang();
return -1;
#else
int ret;

23
arch/arm/mach-rockchip/rk3288/Kconfig
View File

@ -1,5 +1,8 @@
if ROCKCHIP_RK3288
choice
prompt "RK3288 board select"
config TARGET_CHROMEBOOK_JERRY
bool "Google/Rockchip Veyron-Jerry Chromebook"
select BOARD_LATE_INIT
@ -44,6 +47,7 @@ config TARGET_CHROMEBOOK_SPEEDY
config TARGET_EVB_RK3288
bool "Evb-RK3288"
select BOARD_LATE_INIT
select TPL
help
EVB-RK3288 is a RK3288-based development board with 2 USB ports,
HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
@ -125,6 +129,8 @@ config TARGET_TINKER_RK3288
8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
I2C, SPI, UART, GPIOs.
endchoice
config ROCKCHIP_FAST_SPL
bool "Change the CPU to full speed in SPL"
depends on TARGET_CHROMEBOOK_JERRY
@ -134,11 +140,14 @@ config ROCKCHIP_FAST_SPL
voltage. This option is only available on boards which support it
and have the required PMIC code.
config ROCKCHIP_BOOT_MODE_REG
default 0xff730094
config SYS_SOC
default "rk3288"
config SYS_MALLOC_F_LEN
default 0x0800
default 0x2000
config SPL_DRIVERS_MISC_SUPPORT
default y
@ -152,6 +161,18 @@ config SPL_LIBGENERIC_SUPPORT
config SPL_SERIAL_SUPPORT
default y
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl.lds"
config TPL_MAX_SIZE
default 32768
config TPL_STACK
default 0xff718000
config TPL_TEXT_BASE
default 0xff704000
source "board/amarula/vyasa-rk3288/Kconfig"
source "board/chipspark/popmetal_rk3288/Kconfig"

26
arch/arm/mach-rockchip/rk3288/rk3288.c
View File

@ -2,19 +2,45 @@
/*
* Copyright (c) 2016 Rockchip Electronics Co., Ltd
*/
#include <asm/armv7.h>
#include <asm/io.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#define GRF_BASE 0xff770000
#ifdef CONFIG_SPL_BUILD
static void configure_l2ctlr(void)
{
u32 l2ctlr;
l2ctlr = read_l2ctlr();
l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
/*
* Data RAM write latency: 2 cycles
* Data RAM read latency: 2 cycles
* Data RAM setup latency: 1 cycle
* Tag RAM write latency: 1 cycle
* Tag RAM read latency: 1 cycle
* Tag RAM setup latency: 1 cycle
*/
l2ctlr |= (1 << 3 | 1 << 0);
write_l2ctlr(l2ctlr);
}
#endif
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
configure_l2ctlr();
#else
/* We do some SoC one time setting here. */
struct rk3288_grf * const grf = (void *)GRF_BASE;
/* Use rkpwm by default */
rk_setreg(&grf->soc_con2, 1 << 0);
#endif
return 0;
}

1
arch/arm/mach-rockchip/rk3328-board-spl.c
View File

@ -7,7 +7,6 @@
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>

11
arch/arm/mach-rockchip/rk3328/Kconfig
View File

@ -12,11 +12,20 @@ config TARGET_EVB_RK3328
endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff1005c8
config SYS_SOC
default "rk3328"
config SYS_MALLOC_F_LEN
default 0x0800
default 0x2000
config SPL_LIBCOMMON_SUPPORT
default y
config SPL_LIBGENERIC_SUPPORT
default y
source "board/rockchip/evb_rk3328/Kconfig"

33
arch/arm/mach-rockchip/rk3368-board-spl.c
View File

@ -11,6 +11,33 @@
#include <asm/io.h>
#include <asm/arch-rockchip/periph.h>
__weak int arch_cpu_init(void)
{
return 0;
}
#define TIMER_LOAD_COUNT_L 0x00
#define TIMER_LOAD_COUNT_H 0x04
#define TIMER_CONTROL_REG 0x10
#define TIMER_EN 0x1
#define TIMER_FMODE BIT(0)
#define TIMER_RMODE BIT(1)
void rockchip_stimer_init(void)
{
/* If Timer already enabled, don't re-init it */
u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
if (reg & TIMER_EN)
return;
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
TIMER_CONTROL_REG);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
@ -22,6 +49,12 @@ void board_init_f(ulong dummy)
hang();
}
/* Init secure timer */
rockchip_stimer_init();
/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
timer_init();
arch_cpu_init();
preloader_console_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);

123
arch/arm/mach-rockchip/rk3368-board-tpl.c
View File

@ -1,123 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/timer.h>
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
* secure mode (i.e. EL3) and an ATF will eventually be booted before
* starting up the operating system... so we can initialize the SGRF
* here and rely on the ATF installing the final (secure) policy
* later.
*/
static inline uintptr_t sgrf_soc_con_addr(unsigned no)
{
const uintptr_t SGRF_BASE =
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
return SGRF_BASE + sizeof(u32) * no;
}
static inline uintptr_t sgrf_busdmac_addr(unsigned no)
{
const uintptr_t SGRF_BASE =
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
}
static void sgrf_init(void)
{
struct rk3368_cru * const cru =
(struct rk3368_cru * const)rockchip_get_cru();
const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
/* Set all configurable IP to 'non secure'-mode */
rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
/*
* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
* Original comment: "ddr space set no secure mode"
*/
rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
/* Set 'secure dma' to 'non secure'-mode */
rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
dsb(); /* barrier */
rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
dsb(); /* barrier */
udelay(10);
rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("U-Boot TPL board init\n");
#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
/* Reset security, so we can use DMA in the MMC drivers */
sgrf_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
return;
}
}
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}

21
arch/arm/mach-rockchip/rk3368/Kconfig
View File

@ -42,9 +42,21 @@ config TARGET_EVB_PX5
sensor STK3410.
endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff738200
config SYS_SOC
default "rk3368"
config SYS_MALLOC_F_LEN
default 0x2000
config SPL_LIBCOMMON_SUPPORT
default y
config SPL_LIBGENERIC_SUPPORT
default y
source "board/theobroma-systems/lion_rk3368/Kconfig"
source "board/rockchip/sheep_rk3368/Kconfig"
source "board/geekbuying/geekbox/Kconfig"
@ -53,4 +65,13 @@ source "board/rockchip/evb_px5/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds"
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0xff8cffff
config TPL_TEXT_BASE
default 0xff8c1000
endif

75
arch/arm/mach-rockchip/rk3368/rk3368.c
View File

@ -5,12 +5,13 @@
*/
#include <common.h>
#include <syscon.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/grf_rk3368.h>
#include <syscon.h>
#include <asm/arch-rockchip/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
@ -97,6 +98,78 @@ int arch_early_init_r(void)
}
#endif
#ifdef CONFIG_SPL_BUILD
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
* secure mode (i.e. EL3) and an ATF will eventually be booted before
* starting up the operating system... so we can initialize the SGRF
* here and rely on the ATF installing the final (secure) policy
* later.
*/
static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
{
const uintptr_t SGRF_BASE =
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
return SGRF_BASE + sizeof(u32) * no;
}
static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
{
const uintptr_t SGRF_BASE =
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
}
static void sgrf_init(void)
{
struct rk3368_cru * const cru =
(struct rk3368_cru * const)rockchip_get_cru();
const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
/* Set all configurable IP to 'non secure'-mode */
rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
/*
* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
* Original comment: "ddr space set no secure mode"
*/
rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
/* Set 'secure dma' to 'non secure'-mode */
rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
dsb(); /* barrier */
rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
dsb(); /* barrier */
udelay(10);
rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
}
int arch_cpu_init(void)
{
/* Reset security, so we can use DMA in the MMC drivers */
sgrf_init();
return 0;
}
#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{

29
arch/arm/mach-rockchip/rk3399-board-spl.c
View File

@ -21,7 +21,6 @@
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/sys_proto.h>
#include <power/regulator.h>
#include <dm/pinctrl.h>
void board_return_to_bootrom(void)
{
@ -110,30 +109,12 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
"u-boot,spl-boot-device", boot_ofpath);
}
#define TIMER_CHN10_BASE 0xff8680a0
#define TIMER_END_COUNT_L 0x00
#define TIMER_END_COUNT_H 0x04
#define TIMER_INIT_COUNT_L 0x10
#define TIMER_INIT_COUNT_H 0x14
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0 << 1)
#define TIMER_RMODE (1 << 1)
void secure_timer_init(void)
__weak void rockchip_stimer_init(void)
{
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
}
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
struct rk3399_pmusgrf_regs *sgrf;
struct rk3399_grf_regs *grf;
@ -190,13 +171,7 @@ void board_init_f(ulong dummy)
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
secure_timer_init();
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
pr_err("Pinctrl init failed: %d\n", ret);
return;
}
rockchip_stimer_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {

91
arch/arm/mach-rockchip/rk3399-board-tpl.c
View File

@ -1,91 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#define TIMER_CHN10_BASE 0xff8680a0
#define TIMER_END_COUNT_L 0x00
#define TIMER_END_COUNT_H 0x04
#define TIMER_INIT_COUNT_L 0x10
#define TIMER_INIT_COUNT_H 0x14
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0 << 1)
#define TIMER_RMODE (1 << 1)
void secure_timer_init(void)
{
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug("U-Boot TPL board init\n");
#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
secure_timer_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
pr_err("DRAM init failed: %d\n", ret);
return;
}
}
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_board_init(void)
{
puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - "
U_BOOT_TIME " " U_BOOT_TZ ")\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif

23
arch/arm/mach-rockchip/rk3399/Kconfig
View File

@ -64,11 +64,32 @@ config TARGET_CHROMEBOOK_BOB
endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff320300
config SYS_SOC
default "rk3399"
config SYS_MALLOC_F_LEN
default 0x0800
default 0x4000
config SPL_LIBCOMMON_SUPPORT
default y
config SPL_LIBGENERIC_SUPPORT
default y
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_MAX_SIZE
default 188416
config TPL_STACK
default 0xff8effff
config TPL_TEXT_BASE
default 0xff8c2000
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"

29
arch/arm/mach-rockchip/rk3399/rk3399.c
View File

@ -38,6 +38,35 @@ static struct mm_region rk3399_mem_map[] = {
struct mm_region *mem_map = rk3399_mem_map;
#ifdef CONFIG_SPL_BUILD
#define TIMER_END_COUNT_L 0x00
#define TIMER_END_COUNT_H 0x04
#define TIMER_INIT_COUNT_L 0x10
#define TIMER_INIT_COUNT_H 0x14
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE BIT(0)
#define TIMER_RMODE BIT(1)
void rockchip_stimer_init(void)
{
/* If Timer already enabled, don't re-init it */
u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
if (reg & TIMER_EN)
return;
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
TIMER_CONTROL_REG);
}
#endif
int dram_init_banksize(void)
{
size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);

8
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
View File

@ -13,6 +13,7 @@ static const struct udevice_id rk3399_syscon_ids[] = {
{ .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
{ .compatible = "rockchip,rk3399-pmu", .data = ROCKCHIP_SYSCON_PMU },
{ }
};
@ -58,4 +59,11 @@ U_BOOT_DRIVER(rockchip_rk3399_cic) = {
.of_match = rk3399_syscon_ids + 3,
.bind = rk3399_syscon_bind_of_platdata,
};
U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
.name = "rockchip_rk3399_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 4,
.bind = rk3399_syscon_bind_of_platdata,
};
#endif

40
arch/arm/mach-rockchip/rk_timer.c
View File

@ -1,40 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <asm/arch-rockchip/timer.h>
#include <asm/io.h>
#include <linux/types.h>
struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
static uint64_t rockchip_get_ticks(void)
{
uint64_t timebase_h, timebase_l;
timebase_l = readl(&timer_ptr->timer_curr_value0);
timebase_h = readl(&timer_ptr->timer_curr_value1);
return timebase_h << 32 | timebase_l;
}
void rockchip_udelay(unsigned int usec)
{
uint64_t tmp;
/* get timestamp */
tmp = rockchip_get_ticks() + usec_to_tick(usec);
/* loop till event */
while (rockchip_get_ticks() < tmp+1)
;
}
void rockchip_timer_init(void)
{
writel(0xffffffff, &timer_ptr->timer_load_count0);
writel(0xffffffff, &timer_ptr->timer_load_count1);
writel(1, &timer_ptr->timer_ctrl_reg);
}

8
arch/arm/mach-rockchip/rv1108/Kconfig
View File

@ -1,5 +1,8 @@
if ROCKCHIP_RV1108
choice
prompt "RV1108 board select"
config TARGET_EVB_RV1108
bool "EVB_RV1108"
help
@ -22,6 +25,11 @@ config TARGET_ELGIN_RV1108
help
RV1108 ELGIN is a board based on the Rockchip RV1108.
endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0x10300580
config SYS_SOC
default "rv1108"

2
arch/arm/mach-rockchip/spl-boot-order.c
View File

@ -8,7 +8,7 @@
#include <mmc.h>
#include <spl.h>
#if CONFIG_IS_ENABLED(OF_CONTROL)
#if CONFIG_IS_ENABLED(OF_LIBFDT)
/**
* spl_node_to_boot_device() - maps from a DT-node to a SPL boot device
* @node: of_offset of the node

86
arch/arm/mach-rockchip/tpl.c Normal file
View File

@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#define TIMER_LOAD_COUNT_L 0x00
#define TIMER_LOAD_COUNT_H 0x04
#define TIMER_CONTROL_REG 0x10
#define TIMER_EN 0x1
#define TIMER_FMODE BIT(0)
#define TIMER_RMODE BIT(1)
__weak void rockchip_stimer_init(void)
{
/* If Timer already enabled, don't re-init it */
u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
if (reg & TIMER_EN)
return;
#ifndef CONFIG_ARM64
asm volatile("mcr p15, 0, %0, c14, c0, 0"
: : "r"(COUNTER_FREQUENCY));
#endif
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
TIMER_CONTROL_REG);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
U_BOOT_TIME ")\n");
#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
/* Init secure timer */
rockchip_stimer_init();
/* Init ARM arch timer in arch/arm/cpu/ */
timer_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return;
}
}
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}

8
board/amarula/vyasa-rk3288/vyasa-rk3288.c
View File

@ -6,14 +6,6 @@
#include <common.h>
#ifndef CONFIG_TPL_BUILD
#include <spl.h>
void board_boot_order(u32 *spl_boot_list)
{
/* eMMC prior to sdcard. */
spl_boot_list[0] = BOOT_DEVICE_MMC2;
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}
int spl_start_uboot(void)
{

8
board/chipspark/popmetal_rk3288/popmetal-rk3288.c
View File

@ -4,16 +4,8 @@
*/
#include <common.h>
#include <spl.h>
#include <asm/gpio.h>
void board_boot_order(u32 *spl_boot_list)
{
/* eMMC prior to sdcard */
spl_boot_list[0] = BOOT_DEVICE_MMC2;
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}
#define GPIO7A3_HUB_RST 227
int rk_board_late_init(void)

9
board/mqmaker/miqi_rk3288/miqi-rk3288.c
View File

@ -3,12 +3,3 @@
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <spl.h>
void board_boot_order(u32 *spl_boot_list)
{
/* eMMC prior to sdcard. */
spl_boot_list[0] = BOOT_DEVICE_MMC2;
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}

9
board/rockchip/evb_rk3288/evb-rk3288.c
View File

@ -3,12 +3,3 @@
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <spl.h>
void board_boot_order(u32 *spl_boot_list)
{
/* eMMC prior to sdcard. */
spl_boot_list[0] = BOOT_DEVICE_MMC2;
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}

6
board/rockchip/evb_rk3399/README
View File

@ -35,12 +35,6 @@ Get the Source and prebuild binary
> git clone https://github.com/rockchip-linux/rkbin.git
> git clone https://github.com/rockchip-linux/rkdeveloptool.git
Get some prerequisites
======================
You need the Python elftools.elf.elffile library for make_fit_atf.py to work:
> sudo apt-get install python-pyelftools
Compile ATF
===========

9
board/rockchip/fennec_rk3288/fennec-rk3288.c
View File

@ -3,12 +3,3 @@
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <spl.h>
void board_boot_order(u32 *spl_boot_list)
{
/* eMMC prior to sdcard */
spl_boot_list[0] = BOOT_DEVICE_MMC2;
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}

4
board/vamrs/rock960_rk3399/MAINTAINERS
View File

@ -1,11 +1,11 @@
ROCK960-RK3399
M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: board/rockchip/rock960_rk3399
F: include/configs/rock960_rk3399.h
F: configs/rock960-rk3399_defconfig
FICUS EE
M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: configs/ficus-rk3399_defconfig

1
configs/chromebit_mickey_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBIT_MICKEY=y

3
configs/chromebook_bob_defconfig
View File

@ -2,9 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000

1
configs/chromebook_jerry_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_JERRY=y

1
configs/chromebook_minnie_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_MINNIE=y

1
configs/chromebook_speedy_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_SPEEDY=y

7
configs/evb-px5_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3368=y
CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
@ -70,10 +67,6 @@ CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_TPL_TIMER=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_PANIC_HANG=y
CONFIG_SPL_TINY_MEMSET=y

3
configs/evb-rk3229_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x61000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ROCKCHIP_RK322X=y
CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0

10
configs/evb-rk3288_defconfig
View File

@ -1,12 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_EVB_RK3288=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_SPL_SIZE_LIMIT=307200
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
@ -15,9 +13,7 @@ CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_TEXT_BASE=0
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y

2
configs/evb-rk3328_defconfig
View File

@ -1,7 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ROCKCHIP_RK3328=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y

3
configs/evb-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1

1
configs/fennec-rk3288_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_FENNEC_RK3288=y

3
configs/ficus-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_TARGET_ROCK960_RK3399=y

1
configs/firefly-rk3288_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_FIREFLY_RK3288=y

3
configs/firefly-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1

7
configs/lion-rk3368_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3368=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
@ -91,10 +88,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_TPL_TIMER=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZO=y

1
configs/miqi-rk3288_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_MIQI_RK3288=y

3
configs/nanopc-t4-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1

3
configs/nanopi-m4-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1

3
configs/nanopi-neo4-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1

3
configs/orangepi-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1

1
configs/phycore-rk3288_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_PHYCORE_RK3288=y

1
configs/popmetal-rk3288_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_POPMETAL_RK3288=y

3
configs/puma-rk3399_defconfig
View File

@ -2,9 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
CONFIG_TARGET_PUMA_RK3399=y

4
configs/rock-pi-4-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@ -28,6 +25,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y

3
configs/rock64-rk3328_defconfig
View File

@ -2,9 +2,6 @@ CONFIG_SMBIOS_MANUFACTURER="pine64"
CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328"
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ROCKCHIP_RK3328=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000

18
configs/rock960-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_TARGET_ROCK960_RK3399=y
@ -21,7 +18,8 @@ CONFIG_SYS_PROMPT="rock960 => "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@ -34,8 +32,8 @@ CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
@ -47,5 +45,15 @@ CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_DM_ETH=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_USB_XHCI_ROCKCHIP is not set
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y

4
configs/rockpro64-rk3399_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@ -28,6 +25,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y

1
configs/sheep-rk3368_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_ROCKCHIP_RK3368=y
CONFIG_TARGET_SHEEP=y
CONFIG_NR_DRAM_BANKS=1

2
configs/tinker-rk3288_defconfig
View File

@ -1,9 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
CONFIG_TARGET_TINKER_RK3288=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_SIZE_LIMIT=307200

Some files were not shown because too many files have changed in this diff Show More