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arm: zynq: Remove fclk-enable property for cse-nor target

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Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2018-07-20 10:16:21 +02:00
parent 92226b5a6d
commit 7996fcca9d
1 changed files with 0 additions and 1 deletions
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arch/arm/dts/zynq-cse-nor.dts
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@ -56,7 +56,6 @@
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll",
"iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x",