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mmc: matsushita-common: Handle Renesas div-by-1

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On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Marek Vasut 2017-09-26 20:34:35 +02:00
parent f98833dbe6
commit 78773f1467
2 changed files with 3 additions and 1 deletions
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3
drivers/mmc/matsushita-common.c
View File

@ -542,7 +542,8 @@ static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
if (divisor <= 1)
val = MATSU_SD_CLKCTL_DIV1;
val = (priv->caps & MATSU_SD_CAP_RCAR) ?
MATSU_SD_CLKCTL_RCAR_DIV1 : MATSU_SD_CLKCTL_DIV1;
else if (divisor <= 2)
val = MATSU_SD_CLKCTL_DIV2;
else if (divisor <= 4)

1
drivers/mmc/matsushita-common.h
View File

@ -63,6 +63,7 @@
#define MATSU_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
#define MATSU_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
#define MATSU_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
#define MATSU_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
#define MATSU_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
#define MATSU_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
#define MATSU_SD_SIZE 0x04c /* block size */