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This commit is contained in:
Markus Klotzbuecher
2007-08-07 22:30:29 +02:00
committed by Markus Klotzbuecher
parent 9b7464a2c8 b23b547597
commit 78549bbf44
1458 changed files with 48296 additions and 121193 deletions
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4
cpu/74xx_7xx/kgdb.S
View File

@@ -31,7 +31,7 @@
#include <asm/cache.h>
#include <asm/mmu.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
/*
* cache flushing routines for kgdb
@@ -74,4 +74,4 @@ kgdb_flush_cache_range:
SYNC
blr
#endif /* CFG_CMD_KGDB */
#endif

4
cpu/74xx_7xx/start.S
View File

@@ -125,7 +125,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -143,7 +143,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

12
cpu/74xx_7xx/traps.c
View File

@@ -40,7 +40,7 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
@@ -133,7 +133,7 @@ MachineCheckException(struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -166,7 +166,7 @@ MachineCheckException(struct pt_regs *regs)
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -181,7 +181,7 @@ ProgramCheckException(struct pt_regs *regs)
unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
int i, j;
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -204,7 +204,7 @@ ProgramCheckException(struct pt_regs *regs)
void
SoftEmuException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -217,7 +217,7 @@ SoftEmuException(struct pt_regs *regs)
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif

50
cpu/arm720t/lpc2292/Makefile Normal file
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@@ -0,0 +1,50 @@
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = flash.o mmc.o mmc_hw.o spi.o
SOBJS = $(obj)iap_entry.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
# this MUST be compiled as thumb code!
$(SOBJS):
$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

249
cpu/arm720t/lpc2292/flash.c Normal file
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@@ -0,0 +1,249 @@
/*
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
*
* Modified to remove all but the IAP-command related code by
* Gary Jennejohn <garyj@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/hardware.h>
/* IAP commands use 32 bytes at the top of CPU internal sram, we
use 512 bytes below that */
#define COPY_BUFFER_LOCATION 0x40003de0
#define IAP_LOCATION 0x7ffffff1
#define IAP_CMD_PREPARE 50
#define IAP_CMD_COPY 51
#define IAP_CMD_ERASE 52
#define IAP_CMD_CHECK 53
#define IAP_CMD_ID 54
#define IAP_CMD_VERSION 55
#define IAP_CMD_COMPARE 56
#define IAP_RET_CMD_SUCCESS 0
static unsigned long command[5];
static unsigned long result[2];
extern void iap_entry(unsigned long * command, unsigned long * result);
/*-----------------------------------------------------------------------
*
*/
static int get_flash_sector(flash_info_t * info, ulong flash_addr)
{
int i;
for(i = 1; i < (info->sector_count); i++) {
if (flash_addr < (info->start[i]))
break;
}
return (i-1);
}
/*-----------------------------------------------------------------------
* This function assumes that flash_addr is aligned on 512 bytes boundary
* in flash. This function also assumes that prepare have been called
* for the sector in question.
*/
int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
{
int first_sector;
int last_sector;
first_sector = get_flash_sector(info, flash_addr);
last_sector = get_flash_sector(info, flash_addr + 512 - 1);
/* prepare sectors for write */
command[0] = IAP_CMD_PREPARE;
command[1] = first_sector;
command[2] = last_sector;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP prepare failed\n");
return ERR_PROG_ERROR;
}
command[0] = IAP_CMD_COPY;
command[1] = flash_addr;
command[2] = COPY_BUFFER_LOCATION;
command[3] = 512;
command[4] = CFG_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP copy failed\n");
return 1;
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag;
int prot;
int sect;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
flag = disable_interrupts();
printf ("Erasing %d sectors starting at sector %2d.\n"
"This make take some time ... ",
s_last - s_first + 1, s_first);
command[0] = IAP_CMD_PREPARE;
command[1] = s_first;
command[2] = s_last;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP prepare failed\n");
return ERR_PROTECTED;
}
command[0] = IAP_CMD_ERASE;
command[1] = s_first;
command[2] = s_last;
command[3] = CFG_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP erase failed\n");
return ERR_PROTECTED;
}
if (flag)
enable_interrupts();
return ERR_OK;
}
int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
ulong cnt)
{
int first_copy_size;
int last_copy_size;
int first_block;
int last_block;
int nbr_mid_blocks;
uchar memmap_value;
ulong i;
uchar* src_org;
uchar* dst_org;
int ret = ERR_OK;
src_org = src;
dst_org = (uchar*)addr;
first_block = addr / 512;
last_block = (addr + cnt) / 512;
nbr_mid_blocks = last_block - first_block - 1;
first_copy_size = 512 - (addr % 512);
last_copy_size = (addr + cnt) % 512;
debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
(ulong)(first_block * 512),
(ulong)COPY_BUFFER_LOCATION,
(ulong)src,
(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
first_copy_size,
(ulong)COPY_BUFFER_LOCATION,
(ulong)(first_block * 512));
/* copy first block */
memcpy((void*)COPY_BUFFER_LOCATION,
(void*)(first_block * 512), 512);
memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
src, first_copy_size);
lpc2292_copy_buffer_to_flash(info, first_block * 512);
src += first_copy_size;
addr += first_copy_size;
/* copy middle blocks */
for (i = 0; i < nbr_mid_blocks; i++) {
debug("copy middle block: %lX -> %lX 512 bytes, "
"%lX -> %lX 512 bytes\n",
(ulong)src,
(ulong)COPY_BUFFER_LOCATION,
(ulong)COPY_BUFFER_LOCATION,
(ulong)addr);
memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
lpc2292_copy_buffer_to_flash(info, addr);
src += 512;
addr += 512;
}
if (last_copy_size > 0) {
debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
(ulong)(last_block * 512),
(ulong)COPY_BUFFER_LOCATION,
(ulong)src,
(ulong)(COPY_BUFFER_LOCATION),
last_copy_size,
(ulong)COPY_BUFFER_LOCATION,
(ulong)addr);
/* copy last block */
memcpy((void*)COPY_BUFFER_LOCATION,
(void*)(last_block * 512), 512);
memcpy((void*)COPY_BUFFER_LOCATION,
src, last_copy_size);
lpc2292_copy_buffer_to_flash(info, addr);
}
/* verify write */
memmap_value = GET8(MEMMAP);
disable_interrupts();
PUT8(MEMMAP, 01); /* we must make sure that initial 64
bytes are taken from flash when we
do the compare */
for (i = 0; i < cnt; i++) {
if (*dst_org != *src_org){
printf("Write failed. Byte %lX differs\n", i);
ret = ERR_PROG_ERROR;
break;
}
dst_org++;
src_org++;
}
PUT8(MEMMAP, memmap_value);
enable_interrupts();
return ret;
}

7
cpu/arm720t/lpc2292/iap_entry.S Normal file
View File

@@ -0,0 +1,7 @@
IAP_ADDRESS: .word 0x7FFFFFF1
.globl iap_entry
iap_entry:
ldr r2, IAP_ADDRESS
bx r2
mov pc, lr

157
cpu/arm720t/lpc2292/mmc.c Normal file
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@@ -0,0 +1,157 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <part.h>
#include <fat.h>
#include "mmc_hw.h"
#include <asm/arch/spi.h>
#ifdef CONFIG_MMC
#undef MMC_DEBUG
static block_dev_desc_t mmc_dev;
/* these are filled out by a call to mmc_hw_get_parameters */
static int hw_size; /* in kbytes */
static int hw_nr_sects;
static int hw_sect_size; /* in bytes */
block_dev_desc_t * mmc_get_dev(int dev)
{
return (block_dev_desc_t *)(&mmc_dev);
}
unsigned long mmc_block_read(int dev,
unsigned long start,
lbaint_t blkcnt,
void *buffer)
{
unsigned long rc = 0;
unsigned char *p = (unsigned char *)buffer;
unsigned long i;
unsigned long addr = start;
#ifdef MMC_DEBUG
printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
(unsigned long)blkcnt);
#endif
for(i = 0; i < (unsigned long)blkcnt; i++) {
#ifdef MMC_DEBUG
printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
#endif
(void)mmc_read_sector(addr, p);
rc++;
addr++;
p += hw_sect_size;
}
return rc;
}
/*-----------------------------------------------------------------------------
* Read hardware paramterers (sector size, size, number of sectors)
*/
static int mmc_hw_get_parameters(void)
{
unsigned char csddata[16];
unsigned int sizemult;
unsigned int size;
mmc_read_csd(csddata);
hw_sect_size = 1<<(csddata[5] & 0x0f);
size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
hw_nr_sects = (size+1)*(1<<(sizemult+2));
hw_size = hw_nr_sects*hw_sect_size/1024;
#ifdef MMC_DEBUG
printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
"hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
#endif
return 0;
}
int mmc_init(int verbose)
{
int ret = -ENODEV;
if (verbose)
printf("mmc_init\n");
spi_init();
/* this meeds to be done twice */
mmc_hw_init();
udelay(1000);
mmc_hw_init();
mmc_hw_get_parameters();
mmc_dev.if_type = IF_TYPE_MMC;
mmc_dev.part_type = PART_TYPE_DOS;
mmc_dev.dev = 0;
mmc_dev.lun = 0;
mmc_dev.type = 0;
mmc_dev.blksz = hw_sect_size;
mmc_dev.lba = hw_nr_sects;
sprintf((char*)mmc_dev.vendor, "Unknown vendor");
sprintf((char*)mmc_dev.product, "Unknown product");
sprintf((char*)mmc_dev.revision, "N/A");
mmc_dev.removable = 0; /* should be true??? */
mmc_dev.block_read = mmc_block_read;
fat_register_device(&mmc_dev, 1);
ret = 0;
return ret;
}
int mmc_write(uchar * src, ulong dst, int size)
{
#ifdef MMC_DEBUG
printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size);
#endif
/* Since mmc2info always returns 0 this function will never be called */
return 0;
}
int mmc_read(ulong src, uchar * dst, int size)
{
#ifdef MMC_DEBUG
printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size);
#endif
/* Since mmc2info always returns 0 this function will never be called */
return 0;
}
int mmc2info(ulong addr)
{
/* This function is used by cmd_cp to determine if source or destination
address resides on MMC-card or not. We do not support copy to and from
MMC-card so we always return 0. */
return 0;
}
#endif /* CONFIG_MMC */

233
cpu/arm720t/lpc2292/mmc_hw.c Normal file
View File

@@ -0,0 +1,233 @@
/*
This code was original written by Ulrich Radig and modified by
Embedded Artists AB (www.embeddedartists.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spi.h>
#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
#define MMC_Disable() PUT32(IO1SET, 1l << 22)
#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
static unsigned char Write_Command_MMC (unsigned char *CMD);
static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
unsigned short int Bytes);
/* initialize the hardware */
int mmc_hw_init(void)
{
unsigned long a;
unsigned short int Timeout = 0;
unsigned char b;
unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
/* set-up GPIO and SPI */
(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
MMC_Disable();
spi_lock();
spi_set_clock(248);
spi_set_cfg(0, 1, 0);
MMC_Enable();
/* waste some time */
for(a=0; a < 20000; a++)
asm("nop");
/* Put the MMC/SD-card into SPI-mode */
for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
spi_write(0xff);
/* Sends command CMD0 to MMC/SD-card */
while (Write_Command_MMC(CMD) != 1) {
if (Timeout++ > 200) {
MMC_Disable();
spi_unlock();
return(1); /* Abort with command 1 (return 1) */
}
}
/* Sends Command CMD1 an MMC/SD-card */
Timeout = 0;
CMD[0] = 0x41;/* Command 1 */
CMD[5] = 0xFF;
while (Write_Command_MMC(CMD) != 0) {
if (Timeout++ > 200) {
MMC_Disable();
spi_unlock();
return (2); /* Abort with command 2 (return 2) */
}
}
MMC_Disable();
spi_unlock();
return 0;
}
/* ############################################################################
Sends a command to the MMC/SD-card
######################################################################### */
static unsigned char Write_Command_MMC (unsigned char *CMD)
{
unsigned char a, tmp = 0xff;
unsigned short int Timeout = 0;
MMC_Disable();
spi_write(0xFF);
MMC_Enable();
for (a = 0; a < 0x06; a++)
spi_write(*CMD++);
while (tmp == 0xff) {
tmp = spi_read();
if (Timeout++ > 5000)
break;
}
return (tmp);
}
/* ############################################################################
Routine to read the CID register from the MMC/SD-card (16 bytes)
######################################################################### */
void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
int Bytes)
{
unsigned short int a;
spi_lock();
mmc_spi_cfg();
MMC_Enable();
if (Write_Command_MMC(CMD) != 0) {
MMC_Disable();
spi_unlock();
return;
}
while (spi_read() != 0xfe) {};
for (a = 0; a < Bytes; a++)
*Buffer++ = spi_read();
/* Read the CRC-byte */
spi_read(); /* CRC - byte is discarded */
spi_read(); /* CRC - byte is discarded */
/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
MMC_Disable();
spi_unlock();
return;
}
/* ############################################################################
Routine to read a block (512 bytes) from the MMC/SD-card
######################################################################### */
unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
{
/* Command 16 to read aBlocks from the MMC/SD - caed */
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
/* The addres on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
addr = addr << 9; /* addr = addr * 512 */
CMD[1] = ((addr & 0xFF000000) >> 24);
CMD[2] = ((addr & 0x00FF0000) >> 16);
CMD[3] = ((addr & 0x0000FF00) >> 8 );
MMC_Read_Block(CMD, Buffer, 512);
return (0);
}
/* ############################################################################
Routine to write a block (512 byte) to the MMC/SD-card
######################################################################### */
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
{
unsigned char tmp, a;
unsigned short int b;
/* Command 24 to write a block to the MMC/SD - card */
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
/* The addres on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
addr = addr << 9; /* addr = addr * 512 */
CMD[1] = ((addr & 0xFF000000) >> 24);
CMD[2] = ((addr & 0x00FF0000) >> 16);
CMD[3] = ((addr & 0x0000FF00) >> 8 );
spi_lock();
mmc_spi_cfg();
MMC_Enable();
/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
tmp = Write_Command_MMC(CMD);
if (tmp != 0) {
MMC_Disable();
spi_unlock();
return(tmp);
}
/* Do a short delay and send a clock-pulse to the MMC/SD-card */
for (a = 0; a < 100; a++)
spi_read();
/* Send a start byte to the MMC/SD-card */
spi_write(0xFE);
/* Write the block (512 bytes) to the MMC/SD-card */
for (b = 0; b < 512; b++)
spi_write(*Buffer++);
/* write the CRC-Byte */
spi_write(0xFF); /* write a dummy CRC */
spi_write(0xFF); /* CRC code is not used */
/* Wait for MMC/SD-card busy */
while (spi_read() != 0xff) {};
/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
MMC_Disable();
spi_unlock();
return (0);
}
/* #########################################################################
Routine to read the CSD register from the MMC/SD-card (16 bytes)
######################################################################### */
unsigned char mmc_read_csd (unsigned char *Buffer)
{
/* Command to read the CSD register */
unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
MMC_Read_Block(CMD, Buffer, 16);
return (0);
}

29
cpu/arm720t/lpc2292/mmc_hw.h Normal file
View File

@@ -0,0 +1,29 @@
/*
This module implements a linux character device driver for the 24c256 chip.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MMC_HW_
#define _MMC_HW_
unsigned char mmc_read_csd(unsigned char *Buffer);
unsigned char mmc_read_sector (unsigned long addr,
unsigned char *Buffer);
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
int mmc_hw_init(void);
#endif /* _MMC_HW_ */

40
cpu/arm720t/lpc2292/spi.c Normal file
View File

@@ -0,0 +1,40 @@
/*
This module implements an interface to the SPI on the lpc22xx.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spi.h>
unsigned long spi_flags;
unsigned char spi_idle = 0x00;
int spi_init(void)
{
unsigned long pinsel0_value;
/* activate spi pins */
pinsel0_value = GET32(PINSEL0);
pinsel0_value &= ~(0xFFl << 8);
pinsel0_value |= (0x55l << 8);
PUT32(PINSEL0, pinsel0_value);
return 0;
}

4
cpu/arm920t/at91rm9200/bcm5221.c
View File

@@ -32,7 +32,7 @@
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_CMD_NET)
/*
* Name:
@@ -227,6 +227,6 @@ unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
return FALSE;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif
#endif /* CONFIG_DRIVER_ETHER */

4
cpu/arm920t/at91rm9200/dm9161.c
View File

@@ -27,7 +27,7 @@
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_CMD_NET)
/*
* Name:
@@ -220,6 +220,6 @@ UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
return FALSE;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif
#endif /* CONFIG_DRIVER_ETHER */

10
cpu/arm920t/at91rm9200/ether.c
View File

@@ -50,7 +50,7 @@ typedef struct {
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_CMD_NET)
/* alignment as per Errata #11 (64 bytes) is insufficient! */
rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512)));
@@ -265,7 +265,7 @@ void eth_halt (void)
{
};
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
int at91rm9200_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short * value)
{
@@ -284,16 +284,16 @@ int at91rm9200_miiphy_write(char *devname, unsigned char addr,
return 0;
}
#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
#endif
int at91rm9200_miiphy_initialize(bd_t *bis)
{
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
#endif
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif
#endif /* CONFIG_DRIVER_ETHER */

4
cpu/arm920t/at91rm9200/lxt972.c
View File

@@ -33,7 +33,7 @@
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_CMD_NET)
/*
* Name:
@@ -186,6 +186,6 @@ UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
return (lxt972_GetLinkSpeed (p_mac));
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif
#endif /* CONFIG_DRIVER_ETHER */

4
cpu/i386/serial.c
View File

@@ -394,7 +394,7 @@ int serial_buffered_tstc(void)
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
/*
AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
number 0 or number 1
@@ -500,4 +500,4 @@ void kgdb_interruptible(int yes)
return;
}
#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
#endif /* CFG_CMD_KGDB */
#endif

2
cpu/i386/start.S
View File

@@ -149,7 +149,7 @@ data_ok:
.progress3:
/* clear bss section in ram, size must be 4-byte aligned */
movl $_i386boot_bss_start, %eax /* BSS start */
movl $_i386boot_bss_start, %edi /* MK_CHG BSS start */
movl $_i386boot_bss_size, %ecx /* BSS size */
movl %ecx, %eax
andl $3, %eax

2
cpu/ixp/cpu.c
View File

@@ -85,7 +85,7 @@ int cpu_init (void)
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined (CONFIG_PCI)
#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
pci_init();
#endif
return 0;

2
cpu/ixp/npe/npe.c
View File

@@ -682,7 +682,7 @@ int npe_initialize(bd_t * bis)
eth_register(dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write);
#endif

16
cpu/mcf52x2/fec.c
View File

@@ -53,7 +53,7 @@
#undef ET_DEBUG
#undef MII_DEBUG
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
#if defined(CONFIG_CMD_NET) && defined(FEC_ENET)
#ifdef CFG_DISCOVER_PHY
#include <miiphy.h>
@@ -363,7 +363,7 @@ void eth_halt (void)
}
#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
static int phyaddr = -1; /* didn't find a PHY yet */
static uint phytype;
@@ -419,7 +419,7 @@ static uint mii_send (uint mii_cmd)
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
#endif
#if defined(CFG_DISCOVER_PHY)
static void mii_discover_phy (void)
@@ -485,7 +485,7 @@ static void mii_discover_phy (void)
}
#endif /* CFG_DISCOVER_PHY */
#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII)
static int mii_init_done = 0;
@@ -591,13 +591,13 @@ int mcf52x2_miiphy_write (char *devname, unsigned char addr,
return 0;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
#endif /* CFG_CMD_NET, FEC_ENET */
#endif
#endif
int mcf52x2_miiphy_initialize(bd_t *bis)
{
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
#if defined(CONFIG_CMD_NET) && defined(FEC_ENET)
#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII)
miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
#endif
#endif

2
cpu/microblaze/cache.c Executable file → Normal file
View File

@@ -25,7 +25,7 @@
#include <common.h>
#include <asm/asm.h>
#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
#if defined(CONFIG_CMD_CACHE)
int dcache_status (void)
{

4
cpu/microblaze/interrupts.c Executable file → Normal file
View File

@@ -190,7 +190,7 @@ void interrupt_handler (void)
}
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#if defined(CONFIG_CMD_IRQ)
#ifdef CFG_INTC_0
int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
@@ -217,4 +217,4 @@ int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
puts ("Undefined interrupt controller\n");
}
#endif
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
#endif

0
cpu/microblaze/irq.S Executable file → Normal file
View File

8
cpu/mips/au1x00_eth.c
View File

@@ -63,7 +63,7 @@
#include <asm/io.h>
#include <asm/au1x00.h>
#if (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_CMD_MII)
#include <miiphy.h>
#endif
@@ -241,7 +241,7 @@ int au1x00_enet_initialize(bd_t *bis){
eth_register(dev);
#if (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_CMD_MII)
miiphy_register(dev->name,
au1x00_miiphy_read, au1x00_miiphy_write);
#endif
@@ -249,7 +249,7 @@ int au1x00_enet_initialize(bd_t *bis){
return 1;
}
#if (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_CMD_MII)
int au1x00_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short * value)
{
@@ -306,6 +306,6 @@ int au1x00_miiphy_write(char *devname, unsigned char addr,
*mii_control_reg = mii_control;
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
#endif
#endif /* CONFIG_AU1X00 */

46
cpu/mpc512x/Makefile Normal file
View File

@@ -0,0 +1,46 @@
#
# (C) Copyright 2007 DENX Software Engineering
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
cpu/mpc512x/config.mk Normal file
View File

@@ -0,0 +1,25 @@
#
# (C) Copyright 2007 DENX Software Engineering
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e

127
cpu/mpc512x/cpu.c Normal file
View File

@@ -0,0 +1,127 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* (C) Copyright 2007 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* CPU specific code for the MPC512x family.
*
* Derived from the MPC83xx code.
*/
#include <common.h>
#include <command.h>
#include <mpc512x.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
int checkcpu (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
ulong clock = gd->cpu_clk;
u32 pvr = get_pvr ();
u32 spridr = immr->sysconf.spridr;
char buf[32];
puts("CPU: ");
switch (spridr & 0xffff0000) {
case SPR_5121E:
puts ("MPC5121e ");
break;
default:
printf ("Unknown part ID %08x ", spridr & 0xffff0000);
}
printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
switch (pvr & 0xffff0000) {
case PVR_E300C4:
puts ("e300c4 ");
break;
default:
puts ("unknown ");
}
printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock),
gd->csb_clk / 1000000);
return 0;
}
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong msr;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
msr &= ~( MSR_EE | MSR_IR | MSR_DR);
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
/*
* Enable Reset Control Reg - "RSTE" is the magic word that let us go
*/
immap->reset.rpr = 0x52535445;
/* Verify Reset Control Reg is enabled */
while (!((immap->reset.rcer) & RCER_CRE))
;
printf ("Resetting the board.\n");
udelay(200);
/* Perform reset */
immap->reset.rcr = RCR_SWHR;
/* Unreached... */
return 1;
}
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*/
unsigned long get_tbclk (void)
{
ulong tbclk;
tbclk = (gd->bus_clk + 3L) / 4L;
return tbclk;
}
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
/* Reset watchdog */
volatile immap_t *immr = (immap_t *) CFG_IMMR;
immr->wdt.swsrr = 0x556c;
immr->wdt.swsrr = 0xaa39;
if (re_enable)
enable_interrupts ();
}
#endif

87
cpu/mpc512x/cpu_init.c Normal file
View File

@@ -0,0 +1,87 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* (C) Copyright 2007 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Derived from the MPC83xx code.
*
*/
#include <common.h>
#include <mpc512x.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Set up the memory map, initialize registers,
*/
void cpu_init_f (volatile immap_t * im)
{
u32 ips_div;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* system performance tweaking */
#ifdef CFG_ACR_PIPE_DEP
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
(CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
#ifdef CFG_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
(CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
#endif
/* RSR - Reset Status Register - clear all status */
gd->reset_status = im->reset.rsr;
im->reset.rsr = ~(RSR_RES);
/*
* RMR - Reset Mode Register - enable checkstop reset
*/
im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT));
/* Set IPS-CSB divider: IPS = 1/2 CSB */
ips_div = im->clk.scfr[0];
ips_div &= ~(SCFR1_IPS_DIV_MASK);
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
im->clk.scfr[0] = ips_div;
/*
* Enable Time Base/Decrementer
*
* NOTICE: TB needs to be enabled as early as possible in order to
* have udelay() working; if not enabled, usually leads to a hang, like
* during FLASH chip identification etc.
*/
im->sysconf.spcr |= SPCR_TBEN;
}
int cpu_init_r (void)
{
return 0;
}

801
cpu/mpc512x/fec.c Normal file
View File

@@ -0,0 +1,801 @@
/*
* (C) Copyright 2003-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Derived from the MPC8xx FEC driver.
* Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
*/
#include <common.h>
#include <mpc512x.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include "fec.h"
DECLARE_GLOBAL_DATA_PTR;
#define DEBUG 0
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC512x_FEC)
#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
#if (DEBUG & 0x40)
static uint32 local_crc32(char *string, unsigned int crc_value, int len);
#endif
int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
/********************************************************************/
#if (DEBUG & 0x2)
static void mpc512x_fec_phydump (char *devname)
{
uint16 phyStatus, i;
uint8 phyAddr = CONFIG_PHY_ADDR;
uint8 reg_mask[] = {
/* regs to print: 0...8, 21,27,31 */
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
};
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
miiphy_read (devname, phyAddr, i, &phyStatus);
printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
}
#endif
/********************************************************************/
static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
{
int ix;
/*
* Receive BDs init
*/
for (ix = 0; ix < FEC_RBD_NUM; ix++) {
fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix];
fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
fec->bdBase->rbd[ix].dataLength = 0;
}
/*
* have the last RBD to close the ring
*/
fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
fec->rbdIndex = 0;
/*
* Trasmit BDs init
*/
for (ix = 0; ix < FEC_TBD_NUM; ix++) {
fec->bdBase->tbd[ix].status = 0;
}
/*
* Have the last TBD to close the ring
*/
fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
/*
* Initialize some indices
*/
fec->tbdIndex = 0;
fec->usedTbdIndex = 0;
fec->cleanTbdNum = FEC_TBD_NUM;
return 0;
}
/********************************************************************/
static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
{
/*
* Reset buffer descriptor as empty
*/
if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
else
pRbd->status = FEC_RBD_EMPTY;
pRbd->dataLength = 0;
/*
* Increment BD count
*/
fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
/*
* Now, we have an empty RxBD, notify FEC
*/
fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
}
/********************************************************************/
static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
{
volatile FEC_TBD *pUsedTbd;
#if (DEBUG & 0x1)
printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
fec->cleanTbdNum, fec->usedTbdIndex);
#endif
/*
* process all the consumed TBDs
*/
while (fec->cleanTbdNum < FEC_TBD_NUM) {
pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
if (pUsedTbd->status & FEC_TBD_READY) {
#if (DEBUG & 0x20)
printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
#endif
return;
}
/*
* clean this buffer descriptor
*/
if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
pUsedTbd->status = FEC_TBD_WRAP;
else
pUsedTbd->status = 0;
/*
* update some indeces for a correct handling of the TBD ring
*/
fec->cleanTbdNum++;
fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
}
}
/********************************************************************/
static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
{
uint8 currByte; /* byte for which to compute the CRC */
int byte; /* loop - counter */
int bit; /* loop - counter */
uint32 crc = 0xffffffff; /* initial value */
/*
* The algorithm used is the following:
* we loop on each of the six bytes of the provided address,
* and we compute the CRC by left-shifting the previous
* value by one position, so that each bit in the current
* byte of the address may contribute the calculation. If
* the latter and the MSB in the CRC are different, then
* the CRC value so computed is also ex-ored with the
* "polynomium generator". The current byte of the address
* is also shifted right by one bit at each iteration.
* This is because the CRC generatore in hardware is implemented
* as a shift-register with as many ex-ores as the radixes
* in the polynomium. This suggests that we represent the
* polynomiumm itself as a 32-bit constant.
*/
for (byte = 0; byte < 6; byte++) {
currByte = mac[byte];
for (bit = 0; bit < 8; bit++) {
if ((currByte & 0x01) ^ (crc & 0x01)) {
crc >>= 1;
crc = crc ^ 0xedb88320;
} else {
crc >>= 1;
}
currByte >>= 1;
}
}
crc = crc >> 26;
/*
* Set individual hash table register
*/
if (crc >= 32) {
fec->eth->iaddr1 = (1 << (crc - 32));
fec->eth->iaddr2 = 0;
} else {
fec->eth->iaddr1 = 0;
fec->eth->iaddr2 = (1 << crc);
}
/*
* Set physical address
*/
fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
}
/********************************************************************/
static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
{
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_init... Begin\n");
#endif
/* Set interrupt mask register */
fec->eth->imask = 0x00000000;
/* Clear FEC-Lite interrupt event register(IEVENT) */
fec->eth->ievent = 0xffffffff;
/* Set transmit fifo watermark register(X_WMRK), default = 64 */
fec->eth->x_wmrk = 0x0;
/* Set Opcode/Pause Duration Register */
fec->eth->op_pause = 0x00010020;
/* Frame length=1518; MII mode */
fec->eth->r_cntrl = 0x05ee000c;
/* Half-duplex, heartbeat disabled */
fec->eth->x_cntrl = 0x00000000;
/* Enable MIB counters */
fec->eth->mib_control = 0x0;
/* Setup recv fifo start and buff size */
fec->eth->r_fstart = 0x500;
fec->eth->r_buff_size = 0x5e0;
/* Setup BD base addresses */
fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
fec->eth->x_des_start = (uint32)fec->bdBase->tbd;
/* DMA Control */
fec->eth->dma_control = 0xc0000000;
/* Enable FEC */
fec->eth->ecntrl |= 0x00000006;
/* Initilize addresses and status words of BDs */
mpc512x_fec_bd_init (fec);
/* Descriptor polling active */
fec->eth->r_des_active = 0x01000000;
#if (DEBUG & 0x1)
printf("mpc512x_fec_init... Done \n");
#endif
return 1;
}
/********************************************************************/
int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
{
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
int timeout = 1;
uint16 phyStatus;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_init_phy... Begin\n");
#endif
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
fec->eth->ievent = 0xffffffff;
/*
* Set interrupt mask register
*/
fec->eth->imask = 0x00000000;
if (fec->xcv_type != SEVENWIRE) {
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
/*
* Reset PHY, then delay 300ns
*/
miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
udelay (1000);
if (fec->xcv_type == MII10) {
/*
* Force 10Base-T, FDX operation
*/
#if (DEBUG & 0x2)
printf ("Forcing 10 Mbps ethernet link... ");
#endif
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
udelay (10000);
if ((timeout--) == 0) {
#if (DEBUG & 0x2)
printf ("hmmm, should not have waited...");
#endif
break;
}
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf ("=");
#endif
} while ((phyStatus & 0x0004)); /* !link up */
timeout = 1000;
do { /* wait for link status to come back up */
udelay (10000);
if ((timeout--) == 0) {
printf ("failed. Link is down.\n");
break;
}
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf ("+");
#endif
} while (!(phyStatus & 0x0004)); /* !link up */
#if (DEBUG & 0x2)
printf ("done.\n");
#endif
} else { /* MII100 */
/*
* Set the auto-negotiation advertisement register bits
*/
miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
*/
timeout = 50000;
do {
udelay (1000);
if ((timeout--) == 0) {
#if (DEBUG & 0x2)
printf ("PHY auto neg 0 failed...\n");
#endif
return -1;
}
if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
#if (DEBUG & 0x2)
printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
#endif
return -1;
}
} while (!(phyStatus & 0x0004));
#if (DEBUG & 0x2)
printf ("PHY auto neg complete! \n");
#endif
}
}
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc512x_fec_phydump (dev->name);
#endif
#if (DEBUG & 0x1)
printf ("mpc512x_fec_init_phy... Done \n");
#endif
return 1;
}
/********************************************************************/
static void mpc512x_fec_halt (struct eth_device *dev)
{
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
int counter = 0xffff;
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc512x_fec_phydump (dev->name);
#endif
/*
* mask FEC chip interrupts
*/
fec->eth->imask = 0;
/*
* issue graceful stop command to the FEC transmitter if necessary
*/
fec->eth->x_cntrl |= 0x00000001;
/*
* wait for graceful stop to register
*/
while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
/*
* Disable the Ethernet Controller
*/
fec->eth->ecntrl &= 0xfffffffd;
/*
* Issue a reset command to the FEC chip
*/
fec->eth->ecntrl |= 0x1;
/*
* wait at least 16 clock cycles
*/
udelay (10);
#if (DEBUG & 0x3)
printf ("Ethernet task stopped\n");
#endif
}
/********************************************************************/
static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
int data_length)
{
/*
* This routine transmits one frame. This routine only accepts
* 6-byte Ethernet addresses.
*/
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
volatile FEC_TBD *pTbd;
#if (DEBUG & 0x20)
printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
#endif
/*
* Clear Tx BD ring at first
*/
mpc512x_fec_tbd_scrub (fec);
/*
* Check for valid length of data.
*/
if ((data_length > 1500) || (data_length <= 0)) {
return -1;
}
/*
* Check the number of vacant TxBDs.
*/
if (fec->cleanTbdNum < 1) {
#if (DEBUG & 0x20)
printf ("No available TxBDs ...\n");
#endif
return -1;
}
/*
* Get the first TxBD to send the mac header
*/
pTbd = &fec->bdBase->tbd[fec->tbdIndex];
pTbd->dataLength = data_length;
pTbd->dataPointer = (uint32)eth_data;
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
/* Activate transmit Buffer Descriptor polling */
fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */
#if (DEBUG & 0x8)
printf ( "+" );
#endif
fec->cleanTbdNum -= 1;
/*
* wait until frame is sent .
*/
while (pTbd->status & FEC_TBD_READY) {
udelay (10);
#if (DEBUG & 0x8)
printf ("TDB status = %04x\n", pTbd->status);
#endif
}
return 0;
}
/********************************************************************/
static int mpc512x_fec_recv (struct eth_device *dev)
{
/*
* This command pulls one frame from the card
*/
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
unsigned long ievent;
int frame_length, len = 0;
uchar buff[FEC_MAX_PKT_SIZE];
#if (DEBUG & 0x1)
printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
#endif
#if (DEBUG & 0x8)
printf( "-" );
#endif
/*
* Check if any critical events have happened
*/
ievent = fec->eth->ievent;
fec->eth->ievent = ievent;
if (ievent & 0x20060000) {
/* BABT, Rx/Tx FIFO errors */
mpc512x_fec_halt (dev);
mpc512x_fec_init (dev, NULL);
return 0;
}
if (ievent & 0x80000000) {
/* Heartbeat error */
fec->eth->x_cntrl |= 0x00000001;
}
if (ievent & 0x10000000) {
/* Graceful stop complete */
if (fec->eth->x_cntrl & 0x00000001) {
mpc512x_fec_halt (dev);
fec->eth->x_cntrl &= ~0x00000001;
mpc512x_fec_init (dev, NULL);
}
}
if (!(pRbd->status & FEC_RBD_EMPTY)) {
if ((pRbd->status & FEC_RBD_LAST) &&
!(pRbd->status & FEC_RBD_ERR) &&
((pRbd->dataLength - 4) > 14)) {
/*
* Get buffer size
*/
frame_length = pRbd->dataLength - 4;
#if (DEBUG & 0x20)
{
int i;
printf ("recv data hdr:");
for (i = 0; i < 14; i++)
printf ("%x ", *((uint8*)pRbd->dataPointer + i));
printf("\n");
}
#endif
/*
* Fill the buffer and pass it to upper layers
*/
memcpy (buff, (void*)pRbd->dataPointer, frame_length);
NetReceive ((uchar*)buff, frame_length);
len = frame_length;
}
/*
* Reset buffer descriptor as empty
*/
mpc512x_fec_rbd_clean (fec, pRbd);
}
/* Try to fill Buffer Descriptors */
fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
return len;
}
/********************************************************************/
int mpc512x_fec_initialize (bd_t * bis)
{
immap_t *im = (immap_t*) CFG_IMMR;
mpc512x_fec_priv *fec;
struct eth_device *dev;
int i;
char *tmp, *end, env_enetaddr[6];
uint32 *reg;
void * bd;
fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
dev = (struct eth_device *) malloc (sizeof(*dev));
memset (dev, 0, sizeof *dev);
fec->eth = (ethernet_regs *) MPC512X_FEC;
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else
fec->xcv_type = MII10;
# endif
dev->priv = (void *)fec;
dev->iobase = MPC512X_FEC;
dev->init = mpc512x_fec_init;
dev->halt = mpc512x_fec_halt;
dev->send = mpc512x_fec_send;
dev->recv = mpc512x_fec_recv;
sprintf (dev->name, "FEC ETHERNET");
eth_register (dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register (dev->name,
fec512x_miiphy_read, fec512x_miiphy_write);
#endif
/*
* Initialize I\O pins
*/
reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]);
for (i = 0; i < 15; i++)
reg[i] = IOCTRL_MUX_FEC | 0x00000001;
im->io_ctrl.regs[SPDIF_TXCLOCK_IDX] = IOCTRL_MUX_FEC | 0x00000001;
im->io_ctrl.regs[SPDIF_TX_IDX] = IOCTRL_MUX_FEC | 0x00000001;
im->io_ctrl.regs[SPDIF_RX_IDX] = IOCTRL_MUX_FEC | 0x00000001;
/* Clean up space FEC's MIB and FIFO RAM ...*/
memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
/*
* Malloc space for BDs (must be quad word-aligned)
* this pointer is lost, so cannot be freed
*/
bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
/*
* Set interrupt mask register
*/
fec->eth->imask = 0x00000000;
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
fec->eth->ievent = 0xffffffff;
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
* the Linux fec driver will try to work with this garbage.
*/
tmp = getenv ("ethaddr");
if (tmp) {
for (i=0; i<6; i++) {
env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0;
if (tmp)
tmp = (*end) ? end+1 : end;
}
mpc512x_fec_set_hwaddr (fec, env_enetaddr);
fec->eth->gaddr1 = 0x00000000;
fec->eth->gaddr2 = 0x00000000;
}
mpc512x_fec_init_phy (dev, bis);
return 1;
}
/* MII-interface related functions */
/********************************************************************/
int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
uint32 reg; /* convenient holder for the PHY register */
uint32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
/*
* reading from any PHY's register is done by properly
* programming the FEC's MII data register.
*/
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
/*
* wait for the related interrupt
*/
while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
if (timeout == 0) {
#if (DEBUG & 0x2)
printf ("Read MDIO failed...\n");
#endif
return -1;
}
/*
* clear mii interrupt bit
*/
eth->ievent = 0x00800000;
/*
* it's now safe to read the PHY's register
*/
*retVal = (uint16) eth->mii_data;
return 0;
}
/********************************************************************/
int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
{
ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
uint32 reg; /* convenient holder for the PHY register */
uint32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
FEC_MII_DATA_TA | phy | reg | data);
/*
* wait for the MII interrupt
*/
while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
if (timeout == 0) {
#if (DEBUG & 0x2)
printf ("Write MDIO failed...\n");
#endif
return -1;
}
/*
* clear MII interrupt bit
*/
eth->ievent = 0x00800000;
return 0;
}
#if (DEBUG & 0x40)
static uint32 local_crc32 (char *string, unsigned int crc_value, int len)
{
int i;
char c;
unsigned int crc, count;
/*
* crc32 algorithm
*/
/*
* crc = 0xffffffff; * The initialized value should be 0xffffffff
*/
crc = crc_value;
for (i = len; --i >= 0;) {
c = *string++;
for (count = 0; count < 8; count++) {
if ((c & 0x01) ^ (crc & 0x01)) {
crc >>= 1;
crc = crc ^ 0xedb88320;
} else {
crc >>= 1;
}
c >>= 1;
}
}
/*
* In big endian system, do byte swaping for crc value
*/
/**/ return crc;
}
#endif /* DEBUG */
#endif /* CONFIG_MPC512x_FEC */

224
cpu/mpc512x/fec.h Normal file
View File

@@ -0,0 +1,224 @@
/*
* (C) Copyright 2003 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Derived from the MPC8xx driver's header file.
*/
#ifndef __MPC512X_FEC_H
#define __MPC512X_FEC_H
#include <common.h>
#include <mpc512x.h>
typedef unsigned long uint32;
typedef unsigned short uint16;
typedef unsigned char uint8;
typedef struct ethernet_register_set {
/* [10:2]addr = 00 */
/* Control and status Registers (offset 000-1FF) */
volatile uint32 fec_id; /* MBAR_ETH + 0x000 */
volatile uint32 ievent; /* MBAR_ETH + 0x004 */
volatile uint32 imask; /* MBAR_ETH + 0x008 */
volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */
volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
volatile uint32 RES2[6]; /* MBAR_ETH + 0x028-03C */
volatile uint32 mii_data; /* MBAR_ETH + 0x040 */
volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */
volatile uint32 RES3[7]; /* MBAR_ETH + 0x048-060 */
volatile uint32 mib_control; /* MBAR_ETH + 0x064 */
volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */
volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */
volatile uint32 r_hash; /* MBAR_ETH + 0x088 */
volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */
volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */
volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */
volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */
volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */
volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */
volatile uint32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */
volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */
volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */
volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */
volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */
volatile uint32 RES8[6]; /* MBAR_ETH + 0x128-13C */
volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */
volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */
volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */
volatile uint32 r_bound; /* MBAR_ETH + 0x14C */
volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */
volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */
volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */
volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */
volatile uint32 r_buff_size; /* MBAR_ETH + 0x188 */
volatile uint32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */
volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */
volatile uint32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */
/* MIB COUNTERS (Offset 200-2FF) */
volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */
volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */
volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */
volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */
volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */
volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */
volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */
volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */
volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */
volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */
volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */
volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */
volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */
volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */
volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */
volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */
volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */
volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */
volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */
volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */
volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */
volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */
volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */
volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
volatile uint32 RES13[2]; /* MBAR_ETH + 0x278-27C */
volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */
volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */
volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */
volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */
volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */
volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */
volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */
volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */
volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */
volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */
volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */
volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */
volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */
volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */
volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
volatile uint32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */
volatile uint32 RES15[64]; /* MBAR_ETH + 0x300-3FF */
} ethernet_regs;
/* Receive & Transmit Buffer Descriptor definitions */
typedef struct BufferDescriptor {
uint16 status;
uint16 dataLength;
uint32 dataPointer;
} FEC_RBD;
typedef struct {
uint16 status;
uint16 dataLength;
uint32 dataPointer;
} FEC_TBD;
/* private structure */
typedef enum {
SEVENWIRE, /* 7-wire */
MII10, /* MII 10Mbps */
MII100 /* MII 100Mbps */
} xceiver_type;
/* BD Numer definitions */
#define FEC_TBD_NUM 48 /* The user can adjust this value */
#define FEC_RBD_NUM 32 /* The user can adjust this value */
/* packet size limit */
#define FEC_MAX_PKT_SIZE 1536
typedef struct {
uint8 frame[FEC_MAX_PKT_SIZE];
} mpc512x_frame;
typedef struct {
FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */
FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */
mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */
} mpc512x_buff_descs;
typedef struct {
ethernet_regs *eth;
xceiver_type xcv_type; /* transceiver type */
mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
uint16 rbdIndex; /* next receive BD to read */
uint16 tbdIndex; /* next transmit BD to send */
uint16 usedTbdIndex; /* next transmit BD to clean */
uint16 cleanTbdNum; /* the number of available transmit BDs */
} mpc512x_fec_priv;
/* RBD bits definitions */
#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
#define FEC_RBD_LG 0x0020 /* Frame length violation */
#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
#define FEC_RBD_SH 0x0008 /* Short frame */
#define FEC_RBD_CR 0x0004 /* CRC error */
#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
#define FEC_RBD_TR 0x0001 /* Frame is truncated */
#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
FEC_RBD_OV | FEC_RBD_TR)
/* TBD bits definitions */
#define FEC_TBD_READY 0x8000 /* Buffer is ready */
#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
/* MII-related definitios */
#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
#endif /* __MPC512X_FEC_H */

431
cpu/mpc512x/i2c.c Normal file
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/*
* (C) Copyright 2003 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Based on the MPC5xxx code.
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_HARD_I2C
#include <mpc512x.h>
#include <i2c.h>
#define immr ((immap_t *)CFG_IMMR)
/* by default set I2C bus 0 active */
static unsigned int bus_num = 0;
#define I2C_TIMEOUT 100
#define I2C_RETRIES 3
struct mpc512x_i2c_tap {
int scl2tap;
int tap2tap;
};
static int mpc_reg_in(volatile u32 *reg);
static void mpc_reg_out(volatile u32 *reg, int val, int mask);
static int wait_for_bb(void);
static int wait_for_pin(int *status);
static int do_address(uchar chip, char rdwr_flag);
static int send_bytes(uchar chip, char *buf, int len);
static int receive_bytes(uchar chip, char *buf, int len);
static int mpc_get_fdr(int);
static int mpc_reg_in (volatile u32 *reg)
{
int ret = *reg >> 24;
__asm__ __volatile__ ("eieio");
return ret;
}
static void mpc_reg_out (volatile u32 *reg, int val, int mask)
{
int tmp;
if (!mask) {
*reg = val << 24;
} else {
tmp = mpc_reg_in (reg);
*reg = ((tmp & ~mask) | (val & mask)) << 24;
}
__asm__ __volatile__ ("eieio");
return;
}
static int wait_for_bb (void)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int timeout = I2C_TIMEOUT;
int status;
status = mpc_reg_in (&regs->msr);
while (timeout-- && (status & I2C_BB)) {
volatile int temp;
mpc_reg_out (&regs->mcr, I2C_STA, I2C_STA);
temp = mpc_reg_in (&regs->mdr);
mpc_reg_out (&regs->mcr, 0, I2C_STA);
mpc_reg_out (&regs->mcr, 0, 0);
mpc_reg_out (&regs->mcr, I2C_EN, 0);
udelay (1000);
status = mpc_reg_in (&regs->msr);
}
return (status & I2C_BB);
}
static int wait_for_pin (int *status)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int timeout = I2C_TIMEOUT;
*status = mpc_reg_in (&regs->msr);
while (timeout-- && !(*status & I2C_IF)) {
udelay (1000);
*status = mpc_reg_in (&regs->msr);
}
if (!(*status & I2C_IF)) {
return -1;
}
mpc_reg_out (&regs->msr, 0, I2C_IF);
return 0;
}
static int do_address (uchar chip, char rdwr_flag)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int status;
chip <<= 1;
if (rdwr_flag) {
chip |= 1;
}
mpc_reg_out (&regs->mcr, I2C_TX, I2C_TX);
mpc_reg_out (&regs->mdr, chip, 0);
if (wait_for_pin (&status)) {
return -2;
}
if (status & I2C_RXAK) {
return -3;
}
return 0;
}
static int send_bytes (uchar chip, char *buf, int len)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int wrcount;
int status;
for (wrcount = 0; wrcount < len; ++wrcount) {
mpc_reg_out (&regs->mdr, buf[wrcount], 0);
if (wait_for_pin (&status)) {
break;
}
if (status & I2C_RXAK) {
break;
}
}
return !(wrcount == len);
}
static int receive_bytes (uchar chip, char *buf, int len)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int dummy = 1;
int rdcount = 0;
int status;
int i;
mpc_reg_out (&regs->mcr, 0, I2C_TX);
for (i = 0; i < len; ++i) {
buf[rdcount] = mpc_reg_in (&regs->mdr);
if (dummy) {
dummy = 0;
} else {
rdcount++;
}
if (wait_for_pin (&status)) {
return -4;
}
}
mpc_reg_out (&regs->mcr, I2C_TXAK, I2C_TXAK);
buf[rdcount++] = mpc_reg_in (&regs->mdr);
if (wait_for_pin (&status)) {
return -5;
}
mpc_reg_out (&regs->mcr, 0, I2C_TXAK);
return 0;
}
/**************** I2C API ****************/
void i2c_init (int speed, int saddr)
{
int i;
for(i = 0; i < I2C_BUS_CNT; i++){
i2c512x_dev_t *regs = &immr->i2c.dev[i];
mpc_reg_out (&regs->mcr, 0, 0);
/* Set clock */
mpc_reg_out (&regs->mfdr, mpc_get_fdr (speed), 0);
mpc_reg_out (&regs->madr, saddr << 1, 0);
/* Enable module */
mpc_reg_out (&regs->mcr, I2C_EN, I2C_INIT_MASK);
mpc_reg_out (&regs->msr, 0, I2C_IF);
}
/* Disable interrupts */
immr->i2c.icr = 0;
/* Turn off filters */
immr->i2c.mifr = 0;
return;
}
static int mpc_get_fdr (int speed)
{
static int fdr = -1;
if (fdr == -1) {
ulong best_speed = 0;
ulong divider;
ulong ipb, scl;
ulong bestmatch = 0xffffffffUL;
int best_i = 0, best_j = 0, i, j;
int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8};
struct mpc512x_i2c_tap scltap[] = {
{4, 1},
{4, 2},
{6, 4},
{6, 8},
{14, 16},
{30, 32},
{62, 64},
{126, 128}
};
ipb = gd->ipb_clk;
for (i = 7; i >= 0; i--) {
for (j = 7; j >= 0; j--) {
scl = 2 * (scltap[j].scl2tap +
(SCL_Tap[i] - 1) * scltap[j].tap2tap
+ 2);
if (ipb <= speed*scl) {
if ((speed*scl - ipb) < bestmatch) {
bestmatch = speed*scl - ipb;
best_i = i;
best_j = j;
best_speed = ipb/scl;
}
}
}
}
divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
if (gd->flags & GD_FLG_RELOC) {
fdr = divider;
} else {
debug("%ld kHz, \n", best_speed / 1000);
return divider;
}
}
return fdr;
}
int i2c_probe (uchar chip)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int i;
for (i = 0; i < I2C_RETRIES; i++) {
mpc_reg_out (&regs->mcr, I2C_STA, I2C_STA);
if (! do_address (chip, 0)) {
mpc_reg_out (&regs->mcr, 0, I2C_STA);
udelay (500);
break;
}
mpc_reg_out (&regs->mcr, 0, I2C_STA);
udelay (500);
}
return (i == I2C_RETRIES);
}
int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len)
{
char xaddr[4];
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int ret = -1;
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
if (wait_for_bb ()) {
printf ("i2c_read: bus is busy\n");
goto Done;
}
mpc_reg_out (&regs->mcr, I2C_STA, I2C_STA);
if (do_address (chip, 0)) {
printf ("i2c_read: failed to address chip\n");
goto Done;
}
if (send_bytes (chip, &xaddr[4-alen], alen)) {
printf ("i2c_read: send_bytes failed\n");
goto Done;
}
mpc_reg_out (&regs->mcr, I2C_RSTA, I2C_RSTA);
if (do_address (chip, 1)) {
printf ("i2c_read: failed to address chip\n");
goto Done;
}
if (receive_bytes (chip, (char *)buf, len)) {
printf ("i2c_read: receive_bytes failed\n");
goto Done;
}
ret = 0;
Done:
mpc_reg_out (&regs->mcr, 0, I2C_STA);
return ret;
}
int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len)
{
char xaddr[4];
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int ret = -1;
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
if (wait_for_bb ()) {
printf ("i2c_write: bus is busy\n");
goto Done;
}
mpc_reg_out (&regs->mcr, I2C_STA, I2C_STA);
if (do_address (chip, 0)) {
printf ("i2c_write: failed to address chip\n");
goto Done;
}
if (send_bytes (chip, &xaddr[4-alen], alen)) {
printf ("i2c_write: send_bytes failed\n");
goto Done;
}
if (send_bytes (chip, (char *)buf, len)) {
printf ("i2c_write: send_bytes failed\n");
goto Done;
}
ret = 0;
Done:
mpc_reg_out (&regs->mcr, 0, I2C_STA);
return ret;
}
uchar i2c_reg_read (uchar chip, uchar reg)
{
uchar buf;
i2c_read (chip, reg, 1, &buf, 1);
return buf;
}
void i2c_reg_write (uchar chip, uchar reg, uchar val)
{
i2c_write (chip, reg, 1, &val, 1);
return;
}
int i2c_set_bus_num (unsigned int bus)
{
if (bus >= I2C_BUS_CNT) {
return -1;
}
bus_num = bus;
return 0;
}
unsigned int i2c_get_bus_num (void)
{
return bus_num;
}
/* TODO */
unsigned int i2c_get_bus_speed (void)
{
return -1;
}
int i2c_set_bus_speed (unsigned int speed)
{
if (speed != CFG_I2C_SPEED)
return -1;
return 0;
}
#endif /* CONFIG_HARD_I2C */

61
cpu/mpc512x/interrupts.c Normal file
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/*
* (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright 2004 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Derived from the MPC83xx code.
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
struct irq_action {
interrupt_handler_t *handler;
void *arg;
ulong count;
};
int interrupt_init_cpu (unsigned *decrementer_count)
{
*decrementer_count = get_tbclk () / CFG_HZ;
return 0;
}
/*
* Install and free an interrupt handler.
*/
void
irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
{
}
void irq_free_handler (int irq)
{
}
void timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
}

197
cpu/mpc512x/serial.c Normal file
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/*
* (C) Copyright 2000 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Based ont the MPC5200 PSC driver.
* Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
*/
/*
* Minimal serial functions needed to use one of the PSC ports
* as serial console interface.
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_PSC_CONSOLE)
static void fifo_init (volatile psc512x_t *psc)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
/* reset Rx & Tx fifo slice */
psc->rfcmd = PSC_FIFO_RESET_SLICE;
psc->tfcmd = PSC_FIFO_RESET_SLICE;
/* disable Tx & Rx FIFO interrupts */
psc->rfintmask = 0;
psc->tfintmask = 0;
psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
/* enable Tx & Rx FIFO slice */
psc->rfcmd = PSC_FIFO_ENABLE_SLICE;
psc->tfcmd = PSC_FIFO_ENABLE_SLICE;
im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE;
__asm__ volatile ("sync");
}
int serial_init(void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
unsigned long baseclk;
int div;
fifo_init (psc);
/* set MR register to point to MR1 */
psc->command = PSC_SEL_MODE_REG_1;
/* disable Tx/Rx */
psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE;
/* choose the prescaler by 16 for the Tx/Rx clock generation */
psc->psc_clock_select = 0xdd00;
/* switch to UART mode */
psc->sicr = 0;
/* mode register points to mr1 */
/* configure parity, bit length and so on in mode register 1*/
psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
/* now, mode register points to mr2 */
psc->mode = PSC_MODE_1_STOPBIT;
/* calculate dividor for setting PSC CTUR and CTLR registers */
baseclk = (gd->ipb_clk + 8) / 16;
div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
psc->ctur = (div >> 8) & 0xff;
/* set baudrate */
psc->ctlr = div & 0xff;
/* disable all interrupts */
psc->psc_imr = 0;
/* reset and enable Rx/Tx */
psc->command = PSC_RST_RX;
psc->command = PSC_RST_TX;
psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
return 0;
}
void serial_putc (const char c)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
if (c == '\n')
serial_putc ('\r');
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
;
psc->tfdata_8 = c;
}
void serial_putc_raw (const char c)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
;
psc->tfdata_8 = c;
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int serial_getc (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
/* Wait for a character to arrive. */
while (psc->rfstat & PSC_FIFO_EMPTY)
;
return psc->rfdata_8;
}
int serial_tstc (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
return !(psc->rfstat & PSC_FIFO_EMPTY);
}
void serial_setbrg (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
unsigned long baseclk, div;
baseclk = (gd->csb_clk + 8) / 16;
div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
psc->ctur = (div >> 8) & 0xFF;
psc->ctlr = div & 0xff; /* set baudrate */
}
void serial_setrts(int s)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
if (s) {
/* Assert RTS (become LOW) */
psc->op1 = 0x1;
}
else {
/* Negate RTS (become HIGH) */
psc->op0 = 0x1;
}
}
int serial_getcts(void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
return (psc->ip & 0x1) ? 0 : 1;
}
#endif /* CONFIG_PSC_CONSOLE */

135
cpu/mpc512x/speed.c Normal file
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/*
* (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Based on the MPC83xx code.
*/
#include <common.h>
#include <mpc512x.h>
#include <command.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
static int spmf_mult[] = {
68, 1, 12, 16,
20, 24, 28, 32,
36, 40, 44, 48,
52, 56, 60, 64
};
static int cpmf_mult[][2] = {
{0, 1}, {0, 1}, /* 0 and 1 are not valid */
{1, 1}, {3, 2},
{2, 1}, {5, 2},
{3, 1}, {7, 2},
{0, 1}, {0, 1}, /* and all above 7 are not valid too */
{0, 1}, {0, 1},
{0, 1}, {0, 1},
{0, 1}, {0, 1}
};
static int sys_dividors[][2] = {
{2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
{9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
{9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
{15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
{18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
{24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
{29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
};
int get_clocks (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u8 spmf;
u8 cpmf;
u8 sys_div;
u8 ips_div;
u32 ref_clk = CFG_MPC512X_CLKIN;
u32 spll;
u32 sys_clk;
u32 core_clk;
u32 csb_clk;
u32 ips_clk;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
spll = ref_clk * spmf_mult[spmf];
sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
csb_clk = sys_clk / 2;
cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
if (ips_div != 0) {
ips_clk = csb_clk / ips_div;
} else {
/* in case we cannot get a sane IPS divisor, fail gracefully */
ips_clk = 0;
}
gd->ipb_clk = ips_clk;
gd->csb_clk = csb_clk;
gd->cpu_clk = core_clk;
gd->bus_clk = csb_clk;
return 0;
}
/********************************************
* get_bus_freq
* return system bus freq in Hz
*********************************************/
ulong get_bus_freq (ulong dummy)
{
return gd->csb_clk;
}
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
printf ("Clock configuration:\n");
printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000);
printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
printf (" IPS Bus: %4d MHz\n", gd->ipb_clk / 1000000);
printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000);
return 0;
}
U_BOOT_CMD(clocks, 1, 0, do_clocks,
"clocks - print clock configuration\n",
" clocks\n"
);
int prt_mpc512x_clks (void)
{
do_clocks (NULL, 0, 0, NULL);
return (0);
}

780
cpu/mpc512x/start.S Normal file
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@@ -0,0 +1,780 @@
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de>
* Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Based on the MPC83xx code.
*/
/*
* U-Boot - Startup Code for MPC512x based Embedded Boards
*/
#include <config.h>
#include <mpc512x.h>
#include <version.h>
#define CONFIG_521X 1 /* needed for Linux kernel header files*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING "MPC512X"
#endif
/*
* Floating Point enable, Machine Check and Recoverable Interr.
*/
#undef MSR_KERNEL
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif
/* Macros for manipulating CSx_START/STOP */
#define START_REG(start) ((start) >> 16)
#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
/*
* Set up GOT: Global Offset Table
*
* Use r14 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
GOT_ENTRY(__bss_start)
END_GOT
/*
* Magic number and version string
*/
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii " ", CONFIG_IDENT_STRING, "\0"
/*
* Vector Table
*/
.text
. = EXC_OFF_SYS_RESET
.globl _start
/* Start from here after reset/power on */
_start:
li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
b boot_cold
.globl _start_of_vectors
_start_of_vectors:
/* Machine check */
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
lwz r6,GOT(transfer_to_handler)
mtlr r6
blrl
.L_Alignment:
.long AlignmentException - _start + EXC_OFF_SYS_RESET
.long int_return - _start + EXC_OFF_SYS_RESET
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
lwz r6,GOT(transfer_to_handler)
mtlr r6
blrl
.L_ProgramCheck:
.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
.long int_return - _start + EXC_OFF_SYS_RESET
/* Floating Point Unit unavailable exception */
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
/* Decrementer */
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
/* Critical interrupt */
STD_EXCEPTION(0xa00, Critical, UnknownException)
/* System Call */
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
/* Trace interrupt */
STD_EXCEPTION(0xd00, Trace, UnknownException)
/* Performance Monitor interrupt */
STD_EXCEPTION(0xf00, PerfMon, UnknownException)
/* Intruction Translation Miss */
STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
/* Data Load Translation Miss */
STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
/* Data Store Translation Miss */
STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
/* Instruction Address Breakpoint */
STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
/* System Management interrupt */
STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
.globl _end_of_vectors
_end_of_vectors:
. = 0x3000
boot_cold:
/* Save msr contents */
mfmsr r5
/* Set IMMR area to our preferred location */
lis r4, CONFIG_DEFAULT_IMMR@h
lis r3, CFG_IMMR@h
ori r3, r3, CFG_IMMR@l
stw r3, IMMRBAR(r4)
mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
/* Initialise the machine */
bl cpu_early_init
/*
* Set up Local Access Windows:
*
* 1) Boot/CS0 (boot FLASH)
* 2) On-chip SRAM (initial stack purposes)
*/
/* Boot CS/CS0 window range */
lis r3, CFG_IMMR@h
ori r3, r3, CFG_IMMR@l
lis r4, START_REG(CFG_FLASH_BASE)
ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
stw r4, LPCS0AW(r3)
/*
* The SRAM window has a fixed size (256K), so only the start address
* is necessary
*/
lis r4, START_REG(CFG_SRAM_BASE) & 0xff00
stw r4, SRAMBAR(r3)
/*
* According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was
* modified last and an isync
*/
lwz r4, SRAMBAR(r3)
isync
/*
* Set configuration of the Boot/CS0, the SRAM window does not have a
* config register so no params can be set for it
*/
lis r3, (CFG_IMMR + LPC_OFFSET)@h
ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
lis r4, CFG_CS0_CFG@h
ori r4, r4, CFG_CS0_CFG@l
stw r4, CS0_CONFIG(r3)
/* Master enable all CS's */
lis r4, CS_CTRL_ME@h
ori r4, r4, CS_CTRL_ME@l
stw r4, CS_CTRL(r3)
lis r4, (CFG_MONITOR_BASE)@h
ori r4, r4, (CFG_MONITOR_BASE)@l
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
in_flash:
lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
/* let the C-code set up the rest */
/* */
/* Be careful to keep code relocatable & stack humble */
/*------------------------------------------------------*/
GET_GOT /* initialize GOT access */
/* r3: IMMR */
lis r3, CFG_IMMR@h
/* run low-level CPU init code (in Flash) */
bl cpu_init_f
/* r3: BOOTFLAG */
mr r3, r21
/* run 1st part of board init code (in Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
*/
.globl transfer_to_handler
transfer_to_handler:
stw r22,_NIP(r21)
lis r22,MSR_POW@h
andc r23,r23,r22
stw r23,_MSR(r21)
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
mtspr SRR1,r20
mtlr r23
SYNC
rfi /* jump to handler, enable MMU */
int_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SRR0,r2
mtspr SRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfi
/*
* This code initialises the machine, it expects original MSR contents to be in r5.
*/
cpu_early_init:
/* Initialize machine status; enable machine check interrupt */
/*-----------------------------------------------------------*/
li r3, MSR_KERNEL /* Set ME and RI flags */
rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
#ifdef DEBUG
rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
#endif
mtmsr r3
SYNC
mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
lis r3, CFG_IMMR@h
#if defined(CONFIG_WATCHDOG)
/* Initialise the watchdog and reset it */
/*--------------------------------------*/
lis r4, CFG_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3)
/* reset */
li r4, 0x556C
sth r4, SWSRR@l(r3)
li r4, 0x0
ori r4, r4, 0xAA39
sth r4, SWSRR@l(r3)
#else
/* Disable the watchdog */
/*----------------------*/
lwz r4, SWCRR(r3)
/*
* Check to see if it's enabled for disabling: once disabled by s/w
* it's not possible to re-enable it
*/
andi. r4, r4, 0x4
beq 1f
xor r4, r4, r4
stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */
/* Initialize the Hardware Implementation-dependent Registers */
/* HID0 also contains cache control */
/*------------------------------------------------------*/
lis r3, CFG_HID0_INIT@h
ori r3, r3, CFG_HID0_INIT@l
SYNC
mtspr HID0, r3
lis r3, CFG_HID0_FINAL@h
ori r3, r3, CFG_HID0_FINAL@l
SYNC
mtspr HID0, r3
lis r3, CFG_HID2@h
ori r3, r3, CFG_HID2@l
SYNC
mtspr HID2, r3
sync
blr
/* Cache functions.
*
* Note: requires that all cache bits in
* HID0 are in the low half word.
*/
.globl icache_enable
icache_enable:
mfspr r3, HID0
ori r3, r3, HID0_ICE
lis r4, 0
ori r4, r4, HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
mtspr HID0, r4 /* sets enable and invalidate, clears lock */
isync
mtspr HID0, r3 /* clears invalidate */
blr
.globl icache_disable
icache_disable:
mfspr r3, HID0
lis r4, 0
ori r4, r4, HID0_ICE|HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
isync
mtspr HID0, r3 /* clears invalidate */
blr
.globl icache_status
icache_status:
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
blr
.globl dcache_enable
dcache_enable:
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
mtspr HID0, r3 /* no invalidate, unlock */
ori r3, r3, HID0_DCE
ori r5, r3, HID0_DCFI
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
blr
.globl dcache_disable
dcache_disable:
mfspr r3, HID0
lis r4, 0
ori r4, r4, HID0_DCE|HID0_DLOCK
andc r3, r3, r4
ori r4, r3, HID0_DCI
sync
mtspr HID0, r4 /* sets invalidate, clears enable and lock */
sync
mtspr HID0, r3 /* clears invalidate */
blr
.globl dcache_status
dcache_status:
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
blr
.globl get_pvr
get_pvr:
mfspr r3, PVR
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbf */
/* Description: Data Cache block flush */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcDcbf
ppcDcbf:
dcbf r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbi */
/* Description: Data Cache block Invalidate */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcDcbi
ppcDcbi:
dcbi r0,r3
blr
/*--------------------------------------------------------------------------
* Function: ppcDcbz
* Description: Data Cache block zero.
* Input: r3 = effective address
* Output: none.
*-------------------------------------------------------------------------- */
.globl ppcDcbz
ppcDcbz:
dcbz r0,r3
blr
.globl ppcDWstore
ppcDWstore:
lfd 1, 0(r4)
stfd 1, 0(r3)
blr
.globl ppcDWload
ppcDWload:
lfd 1, 0(r3)
stfd 1, 0(r4)
blr
/*-------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
lis r4, CFG_MONITOR_BASE@h /* Source Address */
ori r4, r4, CFG_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
* + Destination Address
*
* Offset:
*/
sub r15, r10, r4
/* First our own GOT */
add r14, r14, r15
/* then the one used by the C code */
add r30, r30, r15
/*
* Now relocate code
*/
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
beq cr1,4f /* In place copy is not necessary */
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
/* copy */
1: lwzu r0,4(r8)
stwu r0,4(r7)
bdnz 1b
addi r0,r5,3
srwi. r0,r0,2
mtctr r0
la r8,-4(r4)
la r7,-4(r3)
/* and compare */
20: lwzu r20,4(r8)
lwzu r21,4(r7)
xor. r22, r20, r21
bne 30f
bdnz 20b
b 4f
/* compare failed */
30: li r3, 0
blr
2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
add r8,r4,r0
add r7,r3,r0
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
blr
in_ram:
/*
* Relocation Function, r14 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr r0
sub r11,r3,r11
addi r3,r3,-4
1: lwzu r0,4(r3)
add r0,r0,r11
stw r0,0(r3)
bdnz 1b
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
2: li r0,__fixup_entries@sectoff@l
lwz r3,GOT(_FIXUP_TABLE_)
cmpwi r0,0
mtctr r0
addi r3,r3,-4
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
add r0,r0,r11
stw r10,0(r3)
stw r0,0(r4)
bdnz 3b
4:
clear_bss:
/*
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
lwz r4,GOT(_end)
cmplw 0, r3, r4
beq 6f
li r0, 0
5:
stw r0, 0(r3)
addi r3, r3, 4
cmplw 0, r3, r4
bne 5b
6:
mr r3, r9 /* Global Data pointer */
mr r4, r10 /* Destination Address */
bl board_init_r
/*
* Copy exception vector code to low memory
*
* r3: dest_addr
* r7: source address, r8: end address, r9: target address
*/
.globl trap_init
trap_init:
lwz r7, GOT(_start)
lwz r8, GOT(_end_of_vectors)
li r9, 0x100 /* reset vector at 0x100 */
cmplw 0, r7, r8
bgelr /* return if r7>=r8 - just in case */
mflr r4 /* save link register */
1:
lwz r0, 0(r7)
stw r0, 0(r9)
addi r7, r7, 4
addi r9, r9, 4
cmplw 0, r7, r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
li r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 2b
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 3b
li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 4b
mfmsr r3 /* now that the vectors have */
lis r7, MSR_IP@h /* relocated into low memory */
ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
andc r3, r3, r7 /* (if it was on) */
SYNC /* Some chip revs need this... */
mtmsr r3
SYNC
mtlr r4 /* restore link register */
blr
/*
* Function: relocate entries for one exception vector
*/
trap_reloc:
lwz r0, 0(r7) /* hdlr ... */
add r0, r0, r3 /* ... += dest_addr */
stw r0, 0(r7)
lwz r0, 4(r7) /* int_return ... */
add r0, r0, r3 /* ... += dest_addr */
stw r0, 4(r7)
blr

205
cpu/mpc512x/traps.c Normal file
View File

@@ -0,0 +1,205 @@
/*
* (C) Copyright 2000 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Derived from the MPC83xx code.
*/
/*
* This file handles the architecture-dependent parts of hardware
* exceptions
*/
#include <common.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long search_exception_table(unsigned long);
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
/*
* Trap & Exception support
*/
void
print_backtrace (unsigned long *sp)
{
int cnt = 0;
unsigned long i;
puts ("Call backtrace: ");
while (sp) {
if ((uint)sp > END_OF_MEM)
break;
i = sp[1];
if (cnt++ % 7 == 0)
putc ('\n');
printf ("%08lX ", i);
if (cnt > 32) break;
sp = (unsigned long *) *sp;
}
putc ('\n');
}
void show_regs (struct pt_regs * regs)
{
int i;
printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0,
regs->msr & MSR_IR ? 1 : 0,
regs->msr & MSR_DR ? 1 : 0);
putc ('\n');
for (i = 0; i < 32; i++) {
if ((i % 8) == 0) {
printf ("GPR%02d: ", i);
}
printf ("%08lX ", regs->gpr[i]);
if ((i % 8) == 7) {
putc ('\n');
}
}
}
void
_exception (int signr, struct pt_regs *regs)
{
show_regs (regs);
print_backtrace ((unsigned long *)regs->gpr[1]);
panic ("Exception at pc %lx signal %d", regs->nip,signr);
}
void
MachineCheckException (struct pt_regs *regs)
{
unsigned long fixup;
if ((fixup = search_exception_table (regs->nip)) != 0) {
regs->nip = fixup;
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
puts ("Machine check.\nCaused by (from msr): ");
printf ("regs %p ",regs);
switch (regs->msr & 0x00FF0000) {
case (0x80000000 >> 10):
puts ("Instruction cache parity signal\n");
break;
case (0x80000000 >> 11):
puts ("Data cache parity signal\n");
break;
case (0x80000000 >> 12):
puts ("Machine check signal\n");
break;
case (0x80000000 >> 13):
puts ("Transfer error ack signal\n");
break;
case (0x80000000 >> 14):
puts ("Data parity signal\n");
break;
case (0x80000000 >> 15):
puts ("Address parity signal\n");
break;
default:
puts ("Unknown values in msr\n");
}
show_regs (regs);
print_backtrace ((unsigned long *)regs->gpr[1]);
panic ("machine check");
}
void
AlignmentException (struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs (regs);
print_backtrace ((unsigned long *)regs->gpr[1]);
panic ("Alignment Exception");
}
void
ProgramCheckException (struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs (regs);
print_backtrace ((unsigned long *)regs->gpr[1]);
panic ("Program Check Exception");
}
void
SoftEmuException (struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs (regs);
print_backtrace ((unsigned long *)regs->gpr[1]);
panic ("Software Emulation Exception");
}
void
UnknownException (struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
_exception (0, regs);
}
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
extern void do_bedbug_breakpoint (struct pt_regs *);
#endif
void
DebugException (struct pt_regs *regs)
{
printf ("Debugger trap at @ %lx\n", regs->nip );
show_regs (regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
do_bedbug_breakpoint (regs);
#endif
}

5
cpu/mpc5xx/config.mk
View File

@@ -28,6 +28,9 @@
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds

4
cpu/mpc5xx/interrupts.c
View File

@@ -178,7 +178,7 @@ void timer_interrupt_cpu (struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#if defined(CONFIG_CMD_IRQ)
/*******************************************************************************
*
* irqinfo - print information about IRQs
@@ -204,4 +204,4 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
#endif

6
cpu/mpc5xx/start.S
View File

@@ -155,7 +155,7 @@ in_flash:
/* Initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r2, CFG_INIT_SP_ADDR@h
ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
/* Note: R0 is still 0 here */
@@ -210,7 +210,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -228,7 +228,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

16
cpu/mpc5xx/traps.c
View File

@@ -36,11 +36,11 @@
#include <command.h>
#include <asm/processor.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
@@ -131,7 +131,7 @@ void MachineCheckException(struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -165,7 +165,7 @@ void MachineCheckException(struct pt_regs *regs)
*/
void AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -179,7 +179,7 @@ void AlignmentException(struct pt_regs *regs)
*/
void ProgramCheckException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -193,7 +193,7 @@ void ProgramCheckException(struct pt_regs *regs)
*/
void SoftEmuException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -208,7 +208,7 @@ void SoftEmuException(struct pt_regs *regs)
*/
void UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -224,7 +224,7 @@ void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}

139
cpu/mpc5xx/u-boot.lds Normal file
View File

@@ -0,0 +1,139 @@
/*
* (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de
* (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc5xx/start.o (.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
/* . = env_start;
.ppcenv :
{
common/environment.o (.ppcenv)
}
*/
}

5
cpu/mpc5xxx/config.mk
View File

@@ -21,7 +21,10 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds

2
cpu/mpc5xxx/cpu_init.c
View File

@@ -198,7 +198,7 @@ int cpu_init_r (void)
/* route critical ints to normal ints */
*(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001;
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
/* load FEC microcode */
loadtask(0, 2);
#endif

27
cpu/mpc5xxx/fec.c
View File

@@ -18,10 +18,10 @@ DECLARE_GLOBAL_DATA_PTR;
/* #define DEBUG 0x28 */
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC5xxx_FEC)
#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
@@ -889,13 +889,20 @@ int mpc5xxx_fec_initialize(bd_t * bis)
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_JUPITER) || defined(CONFIG_MCC200) || \
defined(CONFIG_MOTIONPRO)|| defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
defined(CONFIG_TQM5200) || defined(CONFIG_UC101) || \
defined(CONFIG_V38B)
#if defined(CONFIG_CANMB) || \
defined(CONFIG_CM5200) || \
defined(CONFIG_HMI1001) || \
defined(CONFIG_ICECUBE) || \
defined(CONFIG_INKA4X0) || \
defined(CONFIG_JUPITER) || \
defined(CONFIG_MCC200) || \
defined(CONFIG_MOTIONPRO) || \
defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || \
defined(CONFIG_TOP5200) || \
defined(CONFIG_TQM5200) || \
defined(CONFIG_UC101) || \
defined(CONFIG_V38B)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else
@@ -917,7 +924,7 @@ int mpc5xxx_fec_initialize(bd_t * bis)
sprintf(dev->name, "FEC ETHERNET");
eth_register(dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register (dev->name,
fec5xxx_miiphy_read, fec5xxx_miiphy_write);
#endif

4
cpu/mpc5xxx/ide.c
View File

@@ -24,7 +24,7 @@
*/
#include <common.h>
#ifdef CFG_CMD_IDE
#if defined(CONFIG_CMD_IDE)
#include <mpc5xxx.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -85,4 +85,4 @@ int ide_preinit (void)
return (0);
}
#endif /* CFG_CMD_IDE */
#endif

2
cpu/mpc5xxx/interrupts.c
View File

@@ -310,7 +310,7 @@ void irq_free_handler(int irq)
/****************************************************************************/
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#if defined(CONFIG_CMD_IRQ)
void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
int irq, re_enable;

4
cpu/mpc5xxx/start.S
View File

@@ -208,7 +208,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -227,7 +227,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

16
cpu/mpc5xxx/traps.c
View File

@@ -37,7 +37,7 @@
#include <command.h>
#include <asm/processor.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
@@ -123,7 +123,7 @@ MachineCheckException(struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -158,7 +158,7 @@ MachineCheckException(struct pt_regs *regs)
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -170,7 +170,7 @@ AlignmentException(struct pt_regs *regs)
void
ProgramCheckException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -182,7 +182,7 @@ ProgramCheckException(struct pt_regs *regs)
void
SoftEmuException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -195,7 +195,7 @@ SoftEmuException(struct pt_regs *regs)
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -204,7 +204,7 @@ UnknownException(struct pt_regs *regs)
_exception(0, regs);
}
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
@@ -214,7 +214,7 @@ DebugException(struct pt_regs *regs)
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}

135
cpu/mpc5xxx/u-boot-customlayout.lds Normal file
View File

@@ -0,0 +1,135 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc5xxx/start.o (.text)
cpu/mpc5xxx/traps.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.ppcenv)
*(.text)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

124
cpu/mpc5xxx/u-boot.lds Normal file
View File

@@ -0,0 +1,124 @@
/*
* (C) Copyright 2003-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

5
cpu/mpc8220/config.mk
View File

@@ -21,7 +21,10 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc8220/u-boot.lds

2
cpu/mpc8220/cpu_init.c
View File

@@ -128,7 +128,7 @@ int cpu_init_r (void)
/* route critical ints to normal ints */
*(vu_long *) 0xf0000710 |= 0x00000001;
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
/* load FEC microcode */
loadtask (0, 2);
#endif

6
cpu/mpc8220/fec.c
View File

@@ -15,10 +15,10 @@
#include "fec.h"
#undef DEBUG
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC8220_FEC)
#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
@@ -847,7 +847,7 @@ int mpc8220_fec_initialize (bd_t * bis)
sprintf (dev->name, "FEC ETHERNET");
eth_register (dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register (dev->name,
fec8220_miiphy_read, fec8220_miiphy_write);
#endif

4
cpu/mpc8220/start.S
View File

@@ -169,7 +169,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -188,7 +188,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

16
cpu/mpc8220/traps.c
View File

@@ -37,7 +37,7 @@
#include <command.h>
#include <asm/processor.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler) (struct pt_regs *) = 0;
#endif
@@ -118,7 +118,7 @@ void MachineCheckException (struct pt_regs *regs)
regs->nip = fixup;
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler
&& (*debugger_exception_handler) (regs))
return;
@@ -152,7 +152,7 @@ void MachineCheckException (struct pt_regs *regs)
void AlignmentException (struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler
&& (*debugger_exception_handler) (regs))
return;
@@ -164,7 +164,7 @@ void AlignmentException (struct pt_regs *regs)
void ProgramCheckException (struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler
&& (*debugger_exception_handler) (regs))
return;
@@ -176,7 +176,7 @@ void ProgramCheckException (struct pt_regs *regs)
void SoftEmuException (struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler
&& (*debugger_exception_handler) (regs))
return;
@@ -189,7 +189,7 @@ void SoftEmuException (struct pt_regs *regs)
void UnknownException (struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler
&& (*debugger_exception_handler) (regs))
return;
@@ -199,7 +199,7 @@ void UnknownException (struct pt_regs *regs)
_exception (0, regs);
}
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint (struct pt_regs *);
#endif
@@ -208,7 +208,7 @@ void DebugException (struct pt_regs *regs)
printf ("Debugger trap at @ %lx\n", regs->nip);
show_regs (regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint (regs);
#endif
}

124
cpu/mpc8220/u-boot.lds Normal file
View File

@@ -0,0 +1,124 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc8220/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

5
cpu/mpc824x/config.mk
View File

@@ -21,6 +21,9 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds

4
cpu/mpc824x/start.S
View File

@@ -220,7 +220,7 @@ _start_of_vectors:
/* Alignment exception. */
. = EXC_OFF_ALIGN
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -238,7 +238,7 @@ Alignment:
/* Program check exception */
. = EXC_OFF_PROGRAM
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc824x/traps.c
View File

@@ -175,7 +175,7 @@ UnknownException(struct pt_regs *regs)
_exception(0, regs);
}
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
@@ -185,7 +185,7 @@ DebugException(struct pt_regs *regs)
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}

124
cpu/mpc824x/u-boot.lds Normal file
View File

@@ -0,0 +1,124 @@
/*
* (C) Copyright 2001-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc824x/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

3
cpu/mpc8260/bedbug_603e.c
View File

@@ -10,7 +10,8 @@
#include <bedbug/regs.h>
#include <bedbug/ppc.h>
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260))
#if defined(CONFIG_CMD_BEDBUG) \
&& (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260))
#define MAX_BREAK_POINTS 1

5
cpu/mpc8260/config.mk
View File

@@ -21,7 +21,10 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc8260/u-boot.lds

2
cpu/mpc8260/cpu_init.c
View File

@@ -182,7 +182,7 @@ void cpu_init_f (volatile immap_t * immr)
#endif
/* now restrict to preliminary range */
/* the PS came from the HRCW, don´t change it */
/* the PS came from the HRCW, don<EFBFBD>t change it */
memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK);
memctl->memc_or0 = CFG_OR0_PRELIM;

8
cpu/mpc8260/ether_fcc.c
View File

@@ -47,13 +47,13 @@
#include <config.h>
#include <net.h>
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
static struct ether_fcc_info_s
@@ -393,7 +393,7 @@ int fec_initialize(bd_t *bis)
eth_register(dev);
#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
&& defined(CONFIG_BITBANGMII)
miiphy_register(dev->name,
bb_miiphy_read, bb_miiphy_write);
@@ -1187,4 +1187,4 @@ eth_loopback_test (void)
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
#endif

4
cpu/mpc8260/ether_scc.c
View File

@@ -36,7 +36,7 @@
#include <command.h>
#include <config.h>
#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_ETHER_ON_SCC) && defined(CONFIG_CMD_NET)
#if (CONFIG_ETHER_INDEX == 1)
# define PROFF_ENET PROFF_SCC1
@@ -353,4 +353,4 @@ void restart(void)
}
#endif
#endif /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */
#endif

4
cpu/mpc8260/interrupts.c
View File

@@ -246,7 +246,7 @@ void timer_interrupt_cpu (struct pt_regs *regs)
/****************************************************************************/
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#if defined(CONFIG_CMD_IRQ)
/* ripped this out of ppc4xx/interrupts.c */
@@ -276,4 +276,4 @@ do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
enable_interrupts ();
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
#endif

4
cpu/mpc8260/kgdb.S
View File

@@ -34,7 +34,7 @@
#include <asm/cache.h>
#include <asm/mmu.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
/*
* cache flushing routines for kgdb
@@ -69,4 +69,4 @@ kgdb_flush_cache_range:
SYNC
blr
#endif /* CFG_CMD_KGDB */
#endif

8
cpu/mpc8260/start.S
View File

@@ -279,7 +279,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -298,7 +298,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
@@ -676,13 +676,13 @@ init_debug:
bdnz 1b
/* Load the Instruction Address Breakpoint Register (IABR). */
/* */
/* */
/* The address to load is stored in the first word of dual port */
/* ram and should be preserved while the power is on, so you */
/* can plug addresses into that location then reset the cpu and */
/* this code will load that address into the IABR after the */
/* reset. */
/* */
/* */
/* When the program counter matches the contents of the IABR, */
/* an exception is generated (before the instruction at that */
/* location completes). The vector for this exception is 0x1300 */

16
cpu/mpc8260/traps.c
View File

@@ -37,7 +37,7 @@
#include <asm/processor.h>
#include <asm/m8260_pci.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
@@ -150,7 +150,7 @@ MachineCheckException(struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -186,7 +186,7 @@ MachineCheckException(struct pt_regs *regs)
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -198,7 +198,7 @@ AlignmentException(struct pt_regs *regs)
void
ProgramCheckException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -210,7 +210,7 @@ ProgramCheckException(struct pt_regs *regs)
void
SoftEmuException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -223,7 +223,7 @@ SoftEmuException(struct pt_regs *regs)
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -232,7 +232,7 @@ UnknownException(struct pt_regs *regs)
_exception(0, regs);
}
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
@@ -242,7 +242,7 @@ DebugException(struct pt_regs *regs)
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}

124
cpu/mpc8260/u-boot.lds Normal file
View File

@@ -0,0 +1,124 @@
/*
* (C) Copyright 2001-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc8260/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

5
cpu/mpc83xx/config.mk
View File

@@ -20,7 +20,10 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \
-ffixed-r2 -ffixed-r29 -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds

8
cpu/mpc83xx/cpu.c
View File

@@ -415,7 +415,7 @@ static const struct {
"clock-frequency",
fdt_set_busfreq
},
#ifdef CONFIG_MPC83XX_TSEC1
#ifdef CONFIG_TSEC1
{ "/" OF_SOC "/ethernet@24000,
"mac-address",
fdt_set_eth0
@@ -425,7 +425,7 @@ static const struct {
fdt_set_eth0
},
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
{ "/" OF_SOC "/ethernet@25000,
"mac-address",
fdt_set_eth1
@@ -525,7 +525,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#ifdef CONFIG_MPC83XX_TSEC1
#ifdef CONFIG_TSEC1
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
@@ -535,7 +535,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);

4
cpu/mpc83xx/interrupts.c
View File

@@ -81,7 +81,7 @@ void timer_interrupt_cpu (struct pt_regs *regs)
}
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#if defined(CONFIG_CMD_IRQ)
/* ripped this out of ppc4xx/interrupts.c */
@@ -94,4 +94,4 @@ do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
#endif

4
cpu/mpc83xx/start.S
View File

@@ -263,7 +263,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -282,7 +282,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

14
cpu/mpc83xx/traps.c
View File

@@ -140,7 +140,7 @@ MachineCheckException(struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -176,7 +176,7 @@ MachineCheckException(struct pt_regs *regs)
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -188,7 +188,7 @@ AlignmentException(struct pt_regs *regs)
void
ProgramCheckException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -200,7 +200,7 @@ ProgramCheckException(struct pt_regs *regs)
void
SoftEmuException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -213,7 +213,7 @@ SoftEmuException(struct pt_regs *regs)
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -222,7 +222,7 @@ UnknownException(struct pt_regs *regs)
_exception(0, regs);
}
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
@@ -231,7 +231,7 @@ DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}

122
cpu/mpc83xx/u-boot.lds Normal file
View File

@@ -0,0 +1,122 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc83xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)

2
cpu/mpc85xx/cpu.c
View File

@@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#if defined(CONFIG_MPC85XX_TSEC1)
#if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p)
memcpy(p, bd->bi_enetaddr, 6);

8
cpu/mpc85xx/ether_fcc.c
View File

@@ -48,13 +48,13 @@
#include <config.h>
#include <net.h>
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
#endif
#if defined(CONFIG_CPM2)
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
static struct ether_fcc_info_s
@@ -458,7 +458,7 @@ int fec_initialize(bd_t *bis)
eth_register(dev);
#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
&& defined(CONFIG_BITBANGMII)
miiphy_register(dev->name,
bb_miiphy_read, bb_miiphy_write);
@@ -468,6 +468,6 @@ int fec_initialize(bd_t *bis)
return 1;
}
#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
#endif
#endif /* CONFIG_CPM2 */

4
cpu/mpc85xx/interrupts.c
View File

@@ -144,7 +144,7 @@ void set_timer (ulong t)
timestamp = t;
}
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#if defined(CONFIG_CMD_IRQ)
/*******************************************************************************
*
@@ -159,4 +159,4 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
#endif

4
cpu/mpc85xx/start.S
View File

@@ -457,7 +457,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x0600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -475,7 +475,7 @@ Alignment:
/* Program check exception */
. = 0x0700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

14
cpu/mpc85xx/traps.c
View File

@@ -41,7 +41,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
@@ -74,7 +74,7 @@ static __inline__ unsigned long get_esr(void)
#define ESR_DIZ 0x00400000
#define ESR_U0F 0x00008000
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
@@ -159,7 +159,7 @@ MachineCheckException(struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -192,7 +192,7 @@ MachineCheckException(struct pt_regs *regs)
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -207,7 +207,7 @@ ProgramCheckException(struct pt_regs *regs)
{
long esr_val;
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -244,7 +244,7 @@ PITException(struct pt_regs *regs)
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -259,7 +259,7 @@ DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}

3
cpu/mpc86xx/Makefile
View File

@@ -1,4 +1,5 @@
#
# Copyright 2007 Freescale Semiconductor, Inc.
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao,X.Xiao@motorola.com
#
@@ -30,7 +31,7 @@ LIB = $(obj)lib$(CPU).a
START = start.o #resetvec.o
SOBJS = cache.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
pci.o pcie_indirect.o spd_sdram.o
spd_sdram.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

8
cpu/mpc86xx/cpu.c
View File

@@ -278,7 +278,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#if defined(CONFIG_MPC86XX_TSEC1)
#if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
@@ -287,7 +287,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC2)
#if defined(CONFIG_TSEC2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
@@ -296,7 +296,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enet1addr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC3)
#if defined(CONFIG_TSEC3)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet2addr, 6);
@@ -305,7 +305,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enet2addr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC4)
#if defined(CONFIG_TSEC4)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet3addr, 6);

6
cpu/mpc86xx/interrupts.c
View File

@@ -71,7 +71,7 @@ static __inline__ void set_dec(unsigned long val)
}
/* interrupt is not supported yet */
int interrupt_init_cpu(unsigned *decrementer_count)
int interrupt_init_cpu(unsigned long *decrementer_count)
{
return 0;
}
@@ -107,7 +107,7 @@ int interrupt_init(void)
return ret;
decrementer_count = get_tbclk() / CFG_HZ;
debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n",
debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n",
(get_tbclk() / 1000000),
decrementer_count);
@@ -158,7 +158,7 @@ void timer_interrupt(struct pt_regs *regs)
timestamp++;
ppcDcbf(&timestamp);
ppcDcbf((unsigned long)&timestamp);
/* Restore Decrementer Count */
set_dec(decrementer_count);

146
cpu/mpc86xx/pci.c
View File

@@ -1,146 +0,0 @@
/*
* Copyright (C) Freescale Semiconductor,Inc.
* 2005, 2006. All rights reserved.
*
* Ed Swarthout (ed.swarthout@freescale.com)
* Jason Jin (Jason.jin@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCIE Configuration space access support for PCIE Bridge
*/
#include <common.h>
#include <pci.h>
#if defined(CONFIG_PCI)
void
pci_mpc86xx_init(struct pci_controller *hose)
{
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_pex_t *pcie1 = &immap->im_pex1;
u16 temp16;
u32 temp32;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
uint pcie1_host = (host1_agent == 2) || (host1_agent == 3);
uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 ||
io_sel == 7 || io_sel == 0xf)
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
printf("PCI-EXPRESS 1: Configured as %s \n",
pcie1_agent ? "Agent" : "Host");
if (pcie1_agent)
return; /*Don't scan bus when configured as agent */
printf(" Scanning PCIE bus");
debug("0x%08x=0x%08x ",
&pcie1->pme_msg_det,
pcie1->pme_msg_det);
if (pcie1->pme_msg_det) {
pcie1->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pcie1->pme_msg_det);
}
debug("\n");
} else {
printf("PCI-EXPRESS 1 disabled!\n");
return;
}
/*
* Set first_bus=0 only skipped B0:D0:F0 which is
* a reserved device in M1575, but make it easy for
* most of the scan process.
*/
hose->first_busno = 0x00;
hose->last_busno = 0xfe;
pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
pci_hose_read_config_word(hose,
PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16);
temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_hose_write_config_word(hose,
PCI_BDF(0, 0, 0), PCI_COMMAND, temp16);
pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff);
pci_hose_write_config_byte(hose,
PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80);
pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
&temp32);
temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
temp32);
pcie1->powar1 = 0;
pcie1->powar2 = 0;
pcie1->piwar1 = 0;
pcie1->piwar1 = 0;
pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcie1->powar1 = 0x8004401c; /* 512M MEM space */
pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcie1->potear1 = 0x00000000;
pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
pcie1->powar2 = 0x80088017; /* 16M IO space */
pcie1->potar2 = 0x00000000;
pcie1->potear2 = 0x00000000;
pcie1->pitar1 = 0x00000000;
pcie1->piwbar1 = 0x00000000;
/* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */
pcie1->piwar1 = 0xa0f5501e;
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
pci_set_region(hose->regions + 1,
CFG_PCI1_MEM_BASE,
CFG_PCI1_MEM_PHYS,
CFG_PCI1_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose->regions + 2,
CFG_PCI1_IO_BASE,
CFG_PCI1_IO_PHYS,
CFG_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno);
debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno);
printf("....PCIE1 scan & enumeration done\n");
}
#endif /* CONFIG_PCI */

199
cpu/mpc86xx/pcie_indirect.c
View File

@@ -1,199 +0,0 @@
/*
* Support for indirect PCI bridges.
*
* Copyright (c) Freescale Semiconductor, Inc.
* 2006. All rights reserved.
*
* Jason Jin <Jason.jin@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* partly derived from
* arch/powerpc/platforms/86xx/mpc86xx_pcie.c
*/
#include <common.h>
#ifdef CONFIG_PCI
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#define PCI_CFG_OUT out_be32
#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
static int
indirect_read_config_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
int len,
u32 *val)
{
int bus = PCI_BUS(dev);
volatile unsigned char *cfg_data;
u32 temp;
PEX_FIX;
if (bus == 0xff) {
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000001);
} else {
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000000);
}
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
*/
/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
cfg_data = hose->cfg_data;
PEX_FIX;
temp = in_le32((u32 *) cfg_data);
switch (len) {
case 1:
*val = (temp >> (((offset & 3)) * 8)) & 0xff;
break;
case 2:
*val = (temp >> (((offset & 3)) * 8)) & 0xffff;
break;
default:
*val = temp;
break;
}
return 0;
}
static int
indirect_write_config_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
int len,
u32 val)
{
int bus = PCI_BUS(dev);
volatile unsigned char *cfg_data;
u32 temp;
PEX_FIX;
if (bus == 0xff) {
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000001);
} else {
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000000);
}
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
*/
/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
cfg_data = hose->cfg_data;
switch (len) {
case 1:
PEX_FIX;
temp = in_le32((u32 *) cfg_data);
temp = (temp & ~(0xff << ((offset & 3) * 8))) |
(val << ((offset & 3) * 8));
PEX_FIX;
out_le32((u32 *) cfg_data, temp);
break;
case 2:
PEX_FIX;
temp = in_le32((u32 *) cfg_data);
temp = (temp & ~(0xffff << ((offset & 3) * 8)));
temp |= (val << ((offset & 3) * 8));
PEX_FIX;
out_le32((u32 *) cfg_data, temp);
break;
default:
PEX_FIX;
out_le32((u32 *) cfg_data, val);
break;
}
PEX_FIX;
return 0;
}
static int
indirect_read_config_byte_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u8 *val)
{
u32 val32;
indirect_read_config_pcie(hose, dev, offset, 1, &val32);
*val = (u8) val32;
return 0;
}
static int
indirect_read_config_word_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u16 *val)
{
u32 val32;
indirect_read_config_pcie(hose, dev, offset, 2, &val32);
*val = (u16) val32;
return 0;
}
static int
indirect_read_config_dword_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u32 *val)
{
return indirect_read_config_pcie(hose, dev, offset, 4, val);
}
static int
indirect_write_config_byte_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u8 val)
{
return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val);
}
static int
indirect_write_config_word_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
unsigned short val)
{
return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val);
}
static int
indirect_write_config_dword_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u32 val)
{
return indirect_write_config_pcie(hose, dev, offset, 4, val);
}
void
pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
{
pci_set_ops(hose,
indirect_read_config_byte_pcie,
indirect_read_config_word_pcie,
indirect_read_config_dword_pcie,
indirect_write_config_byte_pcie,
indirect_write_config_word_pcie,
indirect_write_config_dword_pcie);
hose->cfg_addr = (unsigned int *)cfg_addr;
hose->cfg_data = (unsigned char *)cfg_data;
}
#endif /* CONFIG_PCI */

2
cpu/mpc86xx/resetvec.S
View File

@@ -1,2 +0,0 @@
.section .resetvec,"ax"
b _start

4
cpu/mpc86xx/start.S
View File

@@ -116,7 +116,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -134,7 +134,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

12
cpu/mpc86xx/traps.c
View File

@@ -34,7 +34,7 @@
#include <command.h>
#include <asm/processor.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
@@ -122,7 +122,7 @@ MachineCheckException(struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
return;
#endif
@@ -155,7 +155,7 @@ MachineCheckException(struct pt_regs *regs)
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
return;
#endif
@@ -170,7 +170,7 @@ ProgramCheckException(struct pt_regs *regs)
unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
int i, j;
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
return;
#endif
@@ -193,7 +193,7 @@ ProgramCheckException(struct pt_regs *regs)
void
SoftEmuException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
return;
#endif
@@ -205,7 +205,7 @@ SoftEmuException(struct pt_regs *regs)
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
return;
#endif

2
cpu/mpc8xx/bedbug_860.c
View File

@@ -10,7 +10,7 @@
#include <bedbug/ppc.h>
#include <bedbug/type.h>
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_8xx)
#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_8xx)
#define MAX_BREAK_POINTS 2

20
cpu/mpc8xx/fec.c
View File

@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
#undef ET_DEBUG
#if (CONFIG_COMMANDS & CFG_CMD_NET) && \
#if defined(CONFIG_CMD_NET) && \
(defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
@@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(WANT_MII)
#include <miiphy.h>
#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
@@ -182,7 +182,7 @@ int fec_initialize(bd_t *bis)
eth_register(dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name,
fec8xx_miiphy_read, fec8xx_miiphy_write);
#endif
@@ -268,7 +268,7 @@ static int fec_recv (struct eth_device *dev)
length -= 4;
#if (CONFIG_COMMANDS & CFG_CMD_CDP)
#if defined(CONFIG_CMD_CDP)
if ((rx[0] & 1) != 0
&& memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
&& memcmp ((uchar *) rx, NetCDPAddr, 6) != 0)
@@ -608,7 +608,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
#undef ea
#if (CONFIG_COMMANDS & CFG_CMD_CDP)
#if defined(CONFIG_CMD_CDP)
/*
* Turn on multicast address hash table
*/
@@ -787,7 +787,7 @@ static void fec_halt(struct eth_device* dev)
efis->initialized = 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* Make MII read/write commands for the FEC.
*/
@@ -852,7 +852,7 @@ mii_send(uint mii_cmd)
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
#endif
#if defined(CFG_DISCOVER_PHY)
static int mii_discover_phy(struct eth_device *dev)
@@ -926,7 +926,7 @@ static int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
@@ -1020,6 +1020,6 @@ int fec8xx_miiphy_write(char *devname, unsigned char addr,
#endif
return 0;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
#endif
#endif /* CFG_CMD_NET, FEC_ENET */
#endif

4
cpu/mpc8xx/kgdb.S
View File

@@ -34,7 +34,7 @@
#include <asm/cache.h>
#include <asm/mmu.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
/*
* cache flushing routines for kgdb
@@ -71,4 +71,4 @@ kgdb_flush_cache_range:
SYNC
blr
#endif /* CFG_CMD_KGDB */
#endif

4
cpu/mpc8xx/scc.c
View File

@@ -38,7 +38,7 @@
#include <net.h>
#include <command.h>
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET)
#if defined(CONFIG_CMD_NET) && defined(SCC_ENET)
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
@@ -567,4 +567,4 @@ void restart (void)
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
#endif
#endif /* CFG_CMD_NET, SCC_ENET */
#endif

4
cpu/mpc8xx/serial.c
View File

@@ -666,7 +666,7 @@ void enable_putc(void)
}
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
void
kgdb_serial_init(void)
@@ -723,6 +723,6 @@ kgdb_interruptible (int yes)
{
return;
}
#endif /* CFG_CMD_KGDB */
#endif
#endif /* CONFIG_8xx_CONS_NONE */

4
cpu/mpc8xx/start.S
View File

@@ -224,7 +224,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@@ -242,7 +242,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

16
cpu/mpc8xx/traps.c
View File

@@ -36,11 +36,11 @@
#include <command.h>
#include <asm/processor.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
@@ -126,7 +126,7 @@ MachineCheckException(struct pt_regs *regs)
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -159,7 +159,7 @@ MachineCheckException(struct pt_regs *regs)
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -171,7 +171,7 @@ AlignmentException(struct pt_regs *regs)
void
ProgramCheckException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -183,7 +183,7 @@ ProgramCheckException(struct pt_regs *regs)
void
SoftEmuException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -196,7 +196,7 @@ SoftEmuException(struct pt_regs *regs)
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
@@ -210,7 +210,7 @@ DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}

4
cpu/nios/interrupts.c
View File

@@ -173,7 +173,7 @@ void irq_install_handler (int vec, interrupt_handler_t *handler, void *arg)
}
/*************************************************************************/
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#if defined(CONFIG_CMD_IRQ)
int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int vec;
@@ -193,4 +193,4 @@ int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (0);
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
#endif

4
cpu/nios2/interrupts.c
View File

@@ -204,7 +204,7 @@ int interrupt_init (void)
/*************************************************************************/
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#if defined(CONFIG_CMD_IRQ)
int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int i;
@@ -228,4 +228,4 @@ int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (0);
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
#endif

32
cpu/ppc4xx/405gp_pci.c
View File

@@ -77,11 +77,21 @@
#include <asm/processor.h>
#include <pci.h>
#ifdef CONFIG_PCI
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
/*
* Board-specific pci initialization
* Platform code can reimplement pci_pre_init() if needed
*/
int __pci_pre_init(struct pci_controller *hose)
{
return 1;
}
int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
#ifdef CONFIG_PCI
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_PMC405)
ushort pmc405_pci_subsys_deviceid(void);
@@ -191,6 +201,13 @@ void pci_405gp_init(struct pci_controller *hose)
if (hose->pci_fb)
pciauto_region_init(hose->pci_fb);
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
pci_register_hose(hose);
/*--------------------------------------------------------------------------+
@@ -380,7 +397,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3))
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
/*
*As is these functs get called out of flash Not a horrible
@@ -416,14 +433,12 @@ void pci_init_board(void)
#endif
#endif /* CONFIG_PCI */
#endif /* CONFIG_405GP */
/*-----------------------------------------------------------------------------+
* CONFIG_440
*-----------------------------------------------------------------------------*/
#if defined(CONFIG_440) && defined(CONFIG_PCI)
#if defined(CONFIG_440)
static struct pci_controller ppc440_hose = {0};
@@ -496,14 +511,12 @@ void pci_440_init (struct pci_controller *hose)
pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
#if defined(CFG_PCI_PRE_INIT)
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#endif
pci_register_hose( hose );
@@ -575,4 +588,5 @@ void pci_init_board(void)
#endif
}
#endif /* CONFIG_440 & CONFIG_PCI */
#endif /* CONFIG_440 */
#endif /* CONFIG_PCI */

36
cpu/ppc4xx/44x_spd_ddr.c
View File

@@ -70,6 +70,15 @@
#define ONE_BILLION 1000000000
/*
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
*/
void __spd_ddr_init_hang (void)
{
hang ();
}
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
/*-----------------------------------------------------------------------------
| Memory Controller Options 0
+-----------------------------------------------------------------------------*/
@@ -262,7 +271,7 @@ typedef struct bank_param BANKPARMS;
#ifdef CFG_SIMULATE_SPD_EEPROM
extern unsigned char cfg_simulate_spd_eeprom[128];
#endif
void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static unsigned char spd_read(uchar chip, uint addr);
static void get_spd_info(unsigned long *dimm_populated,
@@ -373,7 +382,7 @@ long int spd_sdram(void) {
#ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
/* and program tlb entries for this size (dynamic) */
program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE);
program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
#endif
/*
@@ -467,7 +476,7 @@ static void get_spd_info(unsigned long *dimm_populated,
if (dimm_found == FALSE) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
}
@@ -490,7 +499,7 @@ static void check_mem_type(unsigned long *dimm_populated,
dimm_num);
printf("Only DDR SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
}
}
@@ -510,7 +519,7 @@ static void check_volt_type(unsigned long *dimm_populated,
if (voltage_type != 0x04) {
printf("ERROR: DIMM %lu with unsupported voltage level.\n",
dimm_num);
hang();
spd_ddr_init_hang ();
} else {
debug("DIMM %lu voltage level supported.\n", dimm_num);
}
@@ -581,7 +590,7 @@ static void program_cfg0(unsigned long *dimm_populated,
printf("WARNING: DIMM with datawidth of %lu bits.\n",
data_width);
printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
hang();
spd_ddr_init_hang ();
}
break;
}
@@ -769,7 +778,7 @@ static void program_tr0(unsigned long *dimm_populated,
if ((tcyc_reg & 0x0F) >= 10) {
printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
dimm_num);
hang();
spd_ddr_init_hang ();
}
cycle_time_ns_x_10[cas_index] =
@@ -849,7 +858,7 @@ static void program_tr0(unsigned long *dimm_populated,
printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range.\n");
hang();
spd_ddr_init_hang ();
}
/*
@@ -1008,6 +1017,7 @@ static int short_mem_test(void)
*/
for (i = 0; i < NUMMEMTESTS; i++) {
for (j = 0; j < NUMMEMWORDS; j++) {
/* printf("bank enabled base:%x\n", &membase[j]); */
membase[j] = test[i][j];
ppcDcbf((unsigned long)&(membase[j]));
}
@@ -1160,7 +1170,7 @@ static void program_tr1(void)
*/
if (window_found == FALSE) {
printf("ERROR: Cannot determine a common read delay.\n");
hang();
spd_ddr_init_hang ();
}
/*
@@ -1310,7 +1320,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
printf("ERROR: Unsupported value for the banksize: %d.\n",
bank_size_id);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
switch (num_col_addr) {
@@ -1332,7 +1342,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
printf("ERROR: Unsupported value for number of "
"column addresses: %d.\n", num_col_addr);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
/*
@@ -1340,14 +1350,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
*/
cr |= SDRAM_BXCR_SDBE;
for (i = 0; i < num_banks; i++) {
for (i = 0; i < num_banks; i++) {
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
(4 << 20) * bank_size_id;
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
dimm_num, i, ctrl_bank_num[dimm_num]+i,
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
}
}
}
}

82
cpu/ppc4xx/44x_spd_ddr2.c
View File

@@ -58,8 +58,8 @@
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
#define MAXDIMMS 2
#define MAXRANKS 4
#define MAXDIMMS 2
#define MAXRANKS 4
#define MAXBXCF 4
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
@@ -129,6 +129,16 @@
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
/*
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
*/
void __spd_ddr_init_hang (void)
{
hang ();
}
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
/* Private Structure Definitions */
/* enum only to ease code for cas latency setting */
@@ -144,7 +154,7 @@ typedef enum ddr_cas_id {
* Prototypes
*-----------------------------------------------------------------------------*/
static unsigned long sdram_memsize(void);
void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static void get_spd_info(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
@@ -528,7 +538,7 @@ long int initdram(int board_type)
dram_size = sdram_memsize();
/* and program tlb entries for this size (dynamic) */
program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
/*------------------------------------------------------------------
* DQS calibration.
@@ -582,7 +592,7 @@ static void get_spd_info(unsigned long *dimm_populated,
if (dimm_found == FALSE) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
}
@@ -629,42 +639,42 @@ static void check_mem_type(unsigned long *dimm_populated,
"slot %d.\n", (unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 2:
printf("ERROR: EDO DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 3:
printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 4:
printf("ERROR: SDRAM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 5:
printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 6:
printf("ERROR: SGRAM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 7:
debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
@@ -679,7 +689,7 @@ static void check_mem_type(unsigned long *dimm_populated,
(unsigned int)dimm_num);
printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
}
}
@@ -689,7 +699,7 @@ static void check_mem_type(unsigned long *dimm_populated,
&& (dimm_populated[dimm_num] != SDRAM_NONE)
&& (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
hang();
spd_ddr_init_hang ();
}
}
}
@@ -764,7 +774,7 @@ static void check_frequency(unsigned long *dimm_populated,
(unsigned int)(calc_cycle_time*10));
printf("Replace the DIMM, or change DDR frequency via "
"strapping bits.\n\n");
hang();
spd_ddr_init_hang ();
}
}
}
@@ -796,7 +806,7 @@ static void check_rank_number(unsigned long *dimm_populated,
"slot %d is not supported.\n", dimm_rank, dimm_num);
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
} else
total_rank += dimm_rank;
}
@@ -805,7 +815,7 @@ static void check_rank_number(unsigned long *dimm_populated,
"for all slots.\n", (unsigned int)total_rank);
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
printf("Remove one of the DIMM modules.\n\n");
hang();
spd_ddr_init_hang ();
}
}
}
@@ -830,28 +840,28 @@ static void check_voltage_type(unsigned long *dimm_populated,
printf("This DIMM is 5.0 Volt/TTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
case 0x01:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is LVTTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
case 0x02:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is 1.5 Volt.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
case 0x03:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is 3.3 Volt/TTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
case 0x04:
/* 2.5 Voltage only for DDR1 */
@@ -863,7 +873,7 @@ static void check_voltage_type(unsigned long *dimm_populated,
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
}
}
@@ -1006,13 +1016,13 @@ static void program_copt1(unsigned long *dimm_populated,
if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
if (buf0 != buf1) {
printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
hang();
spd_ddr_init_hang ();
}
}
if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
hang();
spd_ddr_init_hang ();
}
else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_64;
@@ -1020,7 +1030,7 @@ static void program_copt1(unsigned long *dimm_populated,
mcopt1 |= SDRAM_MCOPT1_DMWD_32;
} else {
printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
hang();
spd_ddr_init_hang ();
}
if (ecc_enabled == TRUE)
@@ -1209,7 +1219,7 @@ static void program_initplr(unsigned long *dimm_populated,
break;
default:
printf("ERROR: ucode error on selected_cas value %d", selected_cas);
hang();
spd_ddr_init_hang ();
break;
}
@@ -1241,7 +1251,7 @@ static void program_initplr(unsigned long *dimm_populated,
break;
default:
printf("ERROR: write recovery not support (%d)", write_recovery);
hang();
spd_ddr_init_hang ();
break;
}
#else
@@ -1259,7 +1269,7 @@ static void program_initplr(unsigned long *dimm_populated,
ods = ODS_REDUCED;
} else {
printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
hang();
spd_ddr_init_hang ();
}
mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
@@ -1284,7 +1294,7 @@ static void program_initplr(unsigned long *dimm_populated,
mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
} else {
printf("ERROR: ucode error as unknown DDR type in program_initplr");
hang();
spd_ddr_init_hang ();
}
}
@@ -1389,7 +1399,7 @@ static void program_mode(unsigned long *dimm_populated,
} else {
printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
"in slot %d\n", (unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
}
} else {
/* Convert from hex to decimal */
@@ -1526,7 +1536,7 @@ static void program_mode(unsigned long *dimm_populated,
printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
hang();
spd_ddr_init_hang ();
}
} else { /* DDR2 */
debug("cas_3_0_available=%d\n", cas_3_0_available);
@@ -1549,7 +1559,7 @@ static void program_mode(unsigned long *dimm_populated,
cas_3_0_available, cas_4_0_available, cas_5_0_available);
printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
hang();
spd_ddr_init_hang ();
}
}
@@ -1658,7 +1668,7 @@ static void program_rtr(unsigned long *dimm_populated,
printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
(unsigned int)dimm_num);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
}
@@ -2066,7 +2076,7 @@ static void program_bxcf(unsigned long *dimm_populated,
printf("ERROR: Unsupported value for number of "
"column addresses: %d.\n", (unsigned int)num_col_addr);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
}
@@ -2148,7 +2158,7 @@ static void program_memory_queue(unsigned long *dimm_populated,
printf("ERROR: Unsupported value for the banksize: %d.\n",
(unsigned int)rank_size_id);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
@@ -2693,7 +2703,7 @@ calibration_loop:
printf("\nERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
hang();
spd_ddr_init_hang ();
}
blank_string(strlen(str));
@@ -2849,7 +2859,7 @@ static void test(void)
if (window_found == FALSE) {
printf("ERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
hang();
spd_ddr_init_hang ();
}
/*------------------------------------------------------------------

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