From 22ea278a979e5a73d301eff560296315a8bc2e46 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 3 May 2017 16:22:30 +0200 Subject: [PATCH 01/17] arm64: zynqmp: Remove CPU_RELEASE_ADDR macro CPU_RELEASE_ADDR is used only when CONFIG_ARMV8_MULTIENTRY is enabled. ZynqMP is running ATF which takes care about this that's why no need to have this macro. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index c56cd8c98b..2a8f14bf48 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -29,9 +29,6 @@ #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 1000 -/* Have release address at the end of 256MB for now */ -#define CPU_RELEASE_ADDR 0xFFFFFF0 - #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ From 41f59f6853915291c7451c9e38c196fd5a90bf6a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Feb 2017 08:22:04 +0100 Subject: [PATCH 02/17] microblaze: Build only DTBs for selected target Adding more targets to repository requires some additional changes not simply just adding config file, defconfig and dts. This patch makes this process easier by building only particular DTB which is selected via defconfig that Makefile doesn't need to contain all dts files in the repository. Reported-by: Nathan Rossi Signed-off-by: Michal Simek --- arch/microblaze/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile index 5e70d9e110..f80d8fd850 100644 --- a/arch/microblaze/dts/Makefile +++ b/arch/microblaze/dts/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-y += microblaze-generic.dtb +dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb targets += $(dtb-y) From bd89fba2024305ae301fa7df80848b8d3e13efaf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Feb 2017 09:10:16 +0100 Subject: [PATCH 03/17] arm64: zynqmp: Wire SD1 level shifter mode to SPL Add missing SD boot mode to SPL. zcu102-rev1.0 is supporting this boot mode. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/spl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 0a5f4306e8..7b78d23cf8 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -83,6 +83,7 @@ u32 spl_boot_device(void) case JTAG_MODE: return BOOT_DEVICE_RAM; #ifdef CONFIG_SPL_MMC_SUPPORT + case SD1_LSHFT_MODE: case EMMC_MODE: case SD_MODE: case SD_MODE1: From e3fdf5d05659dbe5ce3f9661a4eb3202005b2be2 Mon Sep 17 00:00:00 2001 From: Jean-Francois Dagenais Date: Sun, 2 Apr 2017 21:44:34 -0400 Subject: [PATCH 04/17] arm64: zynqmp: spl: fix dual SD controller support When enabling both SDHCI controllers, spl_mmc.c would actually choose device sdhci0 even if booted from sdhci1 (boot_device). This is because spl_mmc_get_device_index(boot_device) expects BOOT_DEVICE_MMC2[_2] in order to return index 1 instead of 0. The #if defined(...) statement is copied from board/xilinx/zynqmp/zynqmp.c So the key to properly enabling both controllers as boot sources is defining both CONFIG_ZYNQ_SDHCI0 and CONFIG_ZYNQ_SDHCI1 in your board's include/configs/*.h. Signed-off-by: Jean-Francois Dagenais Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/spl.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 7b78d23cf8..6afa0740d0 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -83,10 +83,15 @@ u32 spl_boot_device(void) case JTAG_MODE: return BOOT_DEVICE_RAM; #ifdef CONFIG_SPL_MMC_SUPPORT - case SD1_LSHFT_MODE: - case EMMC_MODE: - case SD_MODE: case SD_MODE1: + case SD1_LSHFT_MODE: +/* if both controllers enabled, then these two are the second controller */ +#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) + return BOOT_DEVICE_MMC2; +/* else, fall through, the one SDHCI controller that is enabled is number 1 */ +#endif + case SD_MODE: + case EMMC_MODE: return BOOT_DEVICE_MMC1; #endif #ifdef CONFIG_SPL_DFU_SUPPORT @@ -111,6 +116,7 @@ u32 spl_boot_mode(const u32 boot_device) case BOOT_DEVICE_RAM: return 0; case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: return MMCSD_MODE_FS; default: puts("spl: error: unsupported device\n"); From 8bf62ae7da0eea6a152a9d76d009fb79113a3119 Mon Sep 17 00:00:00 2001 From: Jean-Francois Dagenais Date: Sun, 2 Apr 2017 21:44:35 -0400 Subject: [PATCH 05/17] arm64: zynqmp: spl: use given boot_device instead of fetching it again The boot_device argument to spl_boot_mode was massively added without actually modifying the existing functions. This commit actually makes use of the handed value, which is the same. Signed-off-by: Jean-Francois Dagenais Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 6afa0740d0..db7432fd4b 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -112,7 +112,7 @@ u32 spl_boot_device(void) u32 spl_boot_mode(const u32 boot_device) { - switch (spl_boot_device()) { + switch (boot_device) { case BOOT_DEVICE_RAM: return 0; case BOOT_DEVICE_MMC1: From 85a275ba0280342270211ed4d7f666624e3560cb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Feb 2017 10:13:22 +0100 Subject: [PATCH 06/17] arm64: zynqmp: Fix psu_init* external functions In older vivado version some psu_init* files didn't contain mask*() which were missing. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/xil_io.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h index 6bbc000da8..679d234b07 100644 --- a/board/xilinx/zynqmp/xil_io.h +++ b/board/xilinx/zynqmp/xil_io.h @@ -33,12 +33,9 @@ int Xil_In32(unsigned long addr) return readl(addr); } -void mask_delay(u32 delay); void usleep(u32 sleep) { udelay(sleep); } -int mask_poll(u32 add, u32 mask); -int mask_pollOnValue(u32 add, u32 mask, u32 value); #endif /* XIL_IO_H */ From 6b104fead3a1f156644ed8c9be4e0d1641e6a7bb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Oct 2016 14:06:28 +0200 Subject: [PATCH 07/17] arm64: zynqmp: Decrease MALLOC size for SPL Decrease malloc size to 1MB from 256MB. Huge malloc space is adding huge delay in mem_malloc_init() because we are enabling CONFIG_SYS_MALLOC_CLEAR_ON_INIT which clear the whole malloc space. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 2a8f14bf48..52fe9d80d4 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -289,7 +289,7 @@ # define CONFIG_ENV_MAX_ENTRIES 10 # define CONFIG_SYS_SPL_MALLOC_START 0x20000000 -# define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000000 +# define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" From 9e6e2bc2294b88884fff5a0e46d06a2196f19e5f Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 14 May 2017 21:47:02 +0100 Subject: [PATCH 08/17] block: sata: ceva: drop extraneous netdev.h include Drop include of netdev.h as it's a SATA driver not a network driver. Signed-off-by: Peter Robinson Signed-off-by: Michal Simek --- drivers/block/sata_ceva.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c index 65a4bb2099..0c24fce8dc 100644 --- a/drivers/block/sata_ceva.c +++ b/drivers/block/sata_ceva.c @@ -6,7 +6,6 @@ */ #include #include -#include #include #include #include From 1ac237b66b7fdc4b867b1d11597f633639daded7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 25 May 2017 16:08:43 +0200 Subject: [PATCH 09/17] arm64: zynqmp: Add empty sleep.h file for psu_init* compilation psu_init* contain sleep.h header which is not present in u-boot. Instead of keep comment sleep.h in psu_init* it is easier to add empty file which is included. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/sleep.h | 1 + 1 file changed, 1 insertion(+) create mode 100644 board/xilinx/zynqmp/sleep.h diff --git a/board/xilinx/zynqmp/sleep.h b/board/xilinx/zynqmp/sleep.h new file mode 100644 index 0000000000..a962319ffd --- /dev/null +++ b/board/xilinx/zynqmp/sleep.h @@ -0,0 +1 @@ +/* Intentionally empty file for psu_init* */ From b0259c840ecd7ec35ebc5acad061bd6e2bcc847d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 2 Mar 2017 11:02:55 +0100 Subject: [PATCH 10/17] arm64: zynqmp: Add comment about level shifter mode v1 Silicon v1 didn't support SD boot mode with level shifter. Because system can't boot any error message is not shown that's why comment is just a record if someone tries to debug it. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index db7432fd4b..26bf80ec52 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -84,7 +84,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; #ifdef CONFIG_SPL_MMC_SUPPORT case SD_MODE1: - case SD1_LSHFT_MODE: + case SD1_LSHFT_MODE: /* not working on silicon v1 */ /* if both controllers enabled, then these two are the second controller */ #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) return BOOT_DEVICE_MMC2; From 6a1d91be318b44365dfe095a9ca7df1619abefc9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 25 Feb 2017 18:17:11 +0100 Subject: [PATCH 11/17] arm64: zynqmp: Do not map unused OCM/TCM region When OCM or TCM is protected this mapping still exist and it is causing access violation. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/cpu.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index b0f12955a1..280e07ad36 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -37,12 +37,6 @@ static struct mm_region zynqmp_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0xffe00000UL, - .phys = 0xffe00000UL, - .size = 0x00200000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE }, { .virt = 0x400000000UL, .phys = 0x400000000UL, From d84bd9284ea05412928e5b95d4aaebfce18fef7c Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 12 May 2017 15:04:11 +0530 Subject: [PATCH 12/17] arm: zynq: Add Kconfig option for any DDR specific initialization Add Kconfig option for ddr init as this might be required in cases like ddr less systems where we want to skip ddrc init and this option is useful for it. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/mach-zynq/Kconfig | 8 ++++++++ arch/arm/mach-zynq/ddrc.c | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 2529c9ff44..c428ce5cc7 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -24,6 +24,14 @@ config SPL_SPI_FLASH_SUPPORT config SPL_SPI_SUPPORT default y if ZYNQ_QSPI +config ZYNQ_DDRC_INIT + bool "Zynq DDRC initialization" + default y + help + This option used to perform DDR specific initialization + if required. There might be cases like ddr less where we + want to skip ddr init and this option is useful for it. + config SYS_BOARD default "zynq" diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c index d74f8dbbc4..bde52d6562 100644 --- a/arch/arm/mach-zynq/ddrc.c +++ b/arch/arm/mach-zynq/ddrc.c @@ -12,6 +12,9 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_ZYNQ_DDRC_INIT +void zynq_ddrc_init(void) {} +#else /* Control regsiter bitfield definitions */ #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2 @@ -46,3 +49,4 @@ void zynq_ddrc_init(void) puts("ECC disabled "); } } +#endif From e0752bc18422ec0dc93a770e96b1c2f44ee64ed7 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 2 Feb 2017 01:10:46 +0530 Subject: [PATCH 13/17] arm64: zynqmp: Define routines for mmio write and read Define routines of mmio write and read functionalities for zynqmp platform. Also do not call SMC from SPL because SPL is running before ATF in EL3 that's why SMCs can't be called because there is nothing to call. zynqmp_mmio*() are doing direct read/write accesses and this patch does the same. PMUFW is up and running at this time and there is a way to talk to pmufw via IPI but there is no reason to implement IPI stuff in SPL if we need just simple read for getting clock driver to work. Also make invoke_smc as global so that it can be reused in multile places where ever possible. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/cpu.c | 73 ++++++++++++++++++++ arch/arm/include/asm/arch-zynqmp/sys_proto.h | 7 ++ 2 files changed, 80 insertions(+) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 280e07ad36..f7ed179c18 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -98,3 +98,76 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_SILICON; } + +#define ZYNQMP_MMIO_READ 0xC2000014 +#define ZYNQMP_MMIO_WRITE 0xC2000013 + +#ifndef CONFIG_SPL_BUILD +int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, + u32 *ret_payload) +{ + /* + * Added SIP service call Function Identifier + * Make sure to stay in x0 register + */ + struct pt_regs regs; + + regs.regs[0] = pm_api_id; + regs.regs[1] = ((u64)arg1 << 32) | arg0; + regs.regs[2] = ((u64)arg3 << 32) | arg2; + + smc_call(®s); + + if (ret_payload != NULL) { + ret_payload[0] = (u32)regs.regs[0]; + ret_payload[1] = upper_32_bits(regs.regs[0]); + ret_payload[2] = (u32)regs.regs[1]; + ret_payload[3] = upper_32_bits(regs.regs[1]); + ret_payload[4] = (u32)regs.regs[2]; + } + + return regs.regs[0]; +} + +int zynqmp_mmio_write(const u32 address, + const u32 mask, + const u32 value) +{ + return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL); +} + +int zynqmp_mmio_read(const u32 address, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 ret; + + if (!value) + return -EINVAL; + + ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload); + *value = ret_payload[1]; + + return ret; +} +#else +int zynqmp_mmio_write(const u32 address, + const u32 mask, + const u32 value) +{ + u32 data; + u32 value_local = value; + + zynqmp_mmio_read(address, &data); + data &= ~mask; + value_local &= mask; + value_local |= data; + writel(value_local, (ulong)address); + return 0; +} + +int zynqmp_mmio_read(const u32 address, u32 *value) +{ + *value = readl((ulong)address); + return 0; +} +#endif diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 7b11895481..4ae1bb6eef 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -8,6 +8,8 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +#define PAYLOAD_ARG_CNT 5 + int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); @@ -16,4 +18,9 @@ void psu_init(void); void handoff_setup(void); +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); +int zynqmp_mmio_read(const u32 address, u32 *value); +int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, + u32 *ret_payload); + #endif /* _ASM_ARCH_SYS_PROTO_H */ From 7033ae272ed50ccb73434d501098f41430a812a8 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 17 Feb 2017 16:16:01 +0530 Subject: [PATCH 14/17] fpga: zynqmppl: Reuse invoke_smc routine Reuse invoke_smc() routine which is already defined instead of duplicating same at multiple places. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 23039c3eb2..57a4e6c88e 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -10,6 +10,7 @@ #include #include #include +#include #define DUMMY_WORD 0xffffffff @@ -191,25 +192,14 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, return 0; } -static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2) -{ - struct pt_regs regs; - regs.regs[0] = id; - regs.regs[1] = reg0; - regs.regs[2] = reg1; - regs.regs[3] = reg2; - - smc_call(®s); - - return regs.regs[0]; -} - static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { u32 swap; - ulong bin_buf, flags; + ulong bin_buf; int ret; + u32 buf_lo, buf_hi; + u32 ret_payload[PAYLOAD_ARG_CNT]; if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap)) return FPGA_FAIL; @@ -224,9 +214,10 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, else bsize = bsize / 4; - flags = (u32)bsize | ((u64)bstype << 32); - - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0); + buf_lo = (u32)bin_buf; + buf_hi = upper_32_bits(bin_buf); + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, + bstype, ret_payload); if (ret) debug("PL FPGA LOAD fail\n"); From fb4000e87178bf20aeb0d6c6a71b0e25ff8dcda3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 7 Feb 2017 14:32:26 +0100 Subject: [PATCH 15/17] arm64: zynqmp: Check pmufw version If PMUFW version is not v0.3 then panic. ZynqMP switch to CCF based clock driver which requires PMUFW to be present at certain version. This patch ensure that you use correct and tested PMUFW binary. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/cpu.c | 35 ++++++++++++++++++++ arch/arm/include/asm/arch-zynqmp/sys_proto.h | 1 + board/xilinx/zynqmp/zynqmp.c | 8 +++++ include/configs/xilinx_zynqmp.h | 2 ++ 4 files changed, 46 insertions(+) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index f7ed179c18..94ecf90660 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -129,6 +129,41 @@ int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, return regs.regs[0]; } +#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 + +#define ZYNQMP_PM_VERSION_MAJOR 0 +#define ZYNQMP_PM_VERSION_MINOR 3 +#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 +#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF + +#define ZYNQMP_PM_VERSION \ + ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ + ZYNQMP_PM_VERSION_MINOR) + +#if defined(CONFIG_CLK_ZYNQMP) +void zynqmp_pmufw_version(void) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 pm_api_version; + + ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0, + ret_payload); + pm_api_version = ret_payload[1]; + + if (ret) + panic("PMUFW is not found - Please load it!\n"); + + printf("PMUFW:\tv%d.%d\n", + pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT, + pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK); + + if (pm_api_version != ZYNQMP_PM_VERSION) + panic("PMUFW version error. Expected: v%d.%d\n", + ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR); +} +#endif + int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 4ae1bb6eef..d91d98a119 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -18,6 +18,7 @@ void psu_init(void); void handoff_setup(void); +void zynqmp_pmufw_version(void); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_mmio_read(const u32 address, u32 *value); int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 3849b5885d..51a3d9f276 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -113,6 +113,14 @@ static char *zynqmp_get_silicon_idcode_name(void) } #endif +int board_early_init_f(void) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP) + zynqmp_pmufw_version(); +#endif + return 0; +} + #define ZYNQMP_VERSION_SIZE 9 int board_init(void) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 52fe9d80d4..86a4579fbd 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -296,4 +296,6 @@ #endif #endif +#define CONFIG_BOARD_EARLY_INIT_F + #endif /* __XILINX_ZYNQMP_H */ From 988390b8e14f16b5cbc8db057d9dbad45994d3b1 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Wed, 7 Jun 2017 07:42:37 +0200 Subject: [PATCH 16/17] arm: zynq: Move CONFIG_SF_DUAL_FLASH to defconfig Move the only use of CONFIG_SF_DUAL_FLASH to defconfig. This makes the associated topic_miamiplus.h header obsolete, so remove that as well. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- README | 6 ------ configs/topic_miamiplus_defconfig | 3 ++- drivers/mtd/spi/Kconfig | 7 +++++++ include/configs/topic_miami.h | 1 - include/configs/topic_miamiplus.h | 2 -- scripts/config_whitelist.txt | 1 - 6 files changed, 9 insertions(+), 11 deletions(-) delete mode 100644 include/configs/topic_miamiplus.h diff --git a/README b/README index 27a075abbb..2abba91b64 100644 --- a/README +++ b/README @@ -2534,12 +2534,6 @@ The following options need to be configured: Define this option to include a destructive SPI flash test ('sf test'). - CONFIG_SF_DUAL_FLASH Dual flash memories - - Define this option to use dual flash support where two flash - memories can be connected with a given cs line. - Currently Xilinx Zynq qspi supports these type of connections. - - SystemACE Support: CONFIG_SYSTEMACE diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 10762f84e1..535ce6d500 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_VENDOR="topic" -CONFIG_SYS_CONFIG_NAME="topic_miamiplus" +CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" @@ -28,6 +28,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 5ca0a712d8..5700859ff2 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -42,6 +42,13 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SF_DUAL_FLASH + bool "SPI DUAL flash memory support" + depends on SPI_FLASH + help + Enable this option to support two flash memories connected to a single + controller. Currently Xilinx Zynq qspi supports this. + if SPI_FLASH config SPI_FLASH_ATMEL diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index a28922585c..ee46d3ac7e 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -56,7 +56,6 @@ #undef CONFIG_SF_DEFAULT_SPEED #define CONFIG_SF_DEFAULT_SPEED 108000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#undef CONFIG_SF_DUAL_FLASH #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #undef CONFIG_SPI_FLASH_WINBOND #undef CONFIG_SPI_FLASH_ISSI diff --git a/include/configs/topic_miamiplus.h b/include/configs/topic_miamiplus.h deleted file mode 100644 index 46ca6bda04..0000000000 --- a/include/configs/topic_miamiplus.h +++ /dev/null @@ -1,2 +0,0 @@ -#include "topic_miami.h" -#define CONFIG_SF_DUAL_FLASH diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ac7adb20f7..feb430f745 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2284,7 +2284,6 @@ CONFIG_SF_DEFAULT_BUS CONFIG_SF_DEFAULT_CS CONFIG_SF_DEFAULT_MODE CONFIG_SF_DEFAULT_SPEED -CONFIG_SF_DUAL_FLASH CONFIG_SGI_IP28 CONFIG_SH4_PCI CONFIG_SH73A0 From e625881ad77c7cc0ffc39376ae32179c933b3710 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Wed, 7 Jun 2017 07:42:38 +0200 Subject: [PATCH 17/17] arm: zynq: Add support for the topic-miamilite system-on-module The topic-miamilite SoM contains a Zynq xc7z010 SoC, 1GB DDR3L RAM, 64MB dual-parallel QSPI NOR flash and clock sources. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-topic-miamilite.dts | 17 ++ .../zynq/zynq-topic-miamilite/ps7_init_gpl.c | 227 ++++++++++++++++++ .../zynq/zynq-topic-miamilite/ps7_regs.txt | 61 +++++ configs/topic_miamilite_defconfig | 53 ++++ 5 files changed, 359 insertions(+) create mode 100644 arch/arm/dts/zynq-topic-miamilite.dts create mode 100644 board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c create mode 100644 board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt create mode 100644 configs/topic_miamilite_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 61a72186b1..dd6d1daf3e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -127,6 +127,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-microzed.dtb \ zynq-picozed.dtb \ zynq-topic-miami.dtb \ + zynq-topic-miamilite.dtb \ zynq-topic-miamiplus.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm011.dtb \ diff --git a/arch/arm/dts/zynq-topic-miamilite.dts b/arch/arm/dts/zynq-topic-miamilite.dts new file mode 100644 index 0000000000..f88cb4bf98 --- /dev/null +++ b/arch/arm/dts/zynq-topic-miamilite.dts @@ -0,0 +1,17 @@ +/* + * Topic Miami Lite board DTS + * + * Copyright (C) 2017 Topic Embedded Products + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include "zynq-topic-miami.dts" + +/ { + model = "Topic Miami Lite Zynq Board"; + compatible = "topic,miamilite", "xlnx,zynq-7000"; +}; + +&qspi { + is-dual = <1>; +}; diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c new file mode 100644 index 0000000000..ec0cc7d19d --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -0,0 +1,227 @@ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../ps7_init_gpl.h" + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x00113220U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x00024000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00302301U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000C01U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001803U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000C03U), + EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U), + EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FC4C4DU), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003482CU), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00033032U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0002E81FU), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x0002F81AU), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ACU), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B2U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009FU), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009AU), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000127U), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000121U), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000010FU), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000113U), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000ECU), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F2U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DFU), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DAU), + EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x1002E080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000E60U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt new file mode 100644 index 0000000000..db6e642890 --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt @@ -0,0 +1,61 @@ +0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) +0xf8000700 0x202 +0xf8000704 0x202 +0xf8000708 0x202 +0xf800070c 0x202 +0xf8000710 0x202 +0xf8000714 0x202 +0xf8000718 0x202 +0xf800071c 0x200 +0xf8000720 0x202 +0xf8000724 0x202 +0xf8000728 0x202 +0xf800072c 0x202 +0xf8000730 0x202 +0xf8000734 0x202 +0xf8000738 0x12e1 +0xf800073c 0x12e0 +0xf8000740 0x1200 +0xf8000744 0x1200 +0xf8000748 0x1200 +0xf800074c 0x1200 +0xf8000750 0x1200 +0xf8000754 0x1200 +0xf8000758 0x1200 +0xf800075c 0x1200 +0xf8000760 0x1200 +0xf8000764 0x200 +0xf8000768 0x1200 +0xf800076c 0x200 +0xf8000770 0x304 +0xf8000774 0x305 +0xf8000778 0x304 +0xf800077c 0x305 +0xf8000780 0x304 +0xf8000784 0x304 +0xf8000788 0x304 +0xf800078c 0x304 +0xf8000790 0x305 +0xf8000794 0x304 +0xf8000798 0x304 +0xf800079c 0x304 +0xf80007a0 0x380 +0xf80007a4 0x380 +0xf80007a8 0x380 +0xf80007ac 0x380 +0xf80007b0 0x380 +0xf80007b4 0x380 +0xf80007b8 0x1200 +0xf80007bc 0x1200 +0xf80007c0 0x1240 +0xf80007c4 0x1240 +0xf80007c8 0x1240 +0xf80007cc 0x1240 +0xf80007d0 0x1200 +0xf80007d4 0x1200 +0xf8000830 0x380037 +0xf8000834 0x3a0039 +0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz) +0xE000D000 0x800238C1 // QSPI config - divide-by-2 +0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay +0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig new file mode 100644 index 0000000000..a01a82a9a2 --- /dev/null +++ b/configs/topic_miamilite_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="topic" +CONFIG_SYS_CONFIG_NAME="topic_miami" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt" +CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite" +CONFIG_BOOTDELAY=0 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="zynq-uboot> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_RAM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03fd +CONFIG_G_DNL_PRODUCT_NUM=0x0300