arm: move SYS_ARCH_TIMER to KConfig
SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch timer) in U-Boot. At the moment it is mandatory for ARMv8 and used by a few ARMv7 boards. Add a proper Kconfig symbol to express this dependency properly, allowing certain board configuration to later disable arch timer in case there are any problems with it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [tuomas: rebase + fix conflicts and resync with moveconfig & use select] Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
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@ -242,6 +242,16 @@ config SYS_CACHELINE_SIZE
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default 64 if SYS_CACHE_SHIFT_6
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default 32 if SYS_CACHE_SHIFT_5
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config SYS_ARCH_TIMER
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bool "ARM Generic Timer support"
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depends on CPU_V7 || ARM64
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default y if ARM64
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help
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The ARM Generic Timer (aka arch-timer) provides an architected
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interface to a timer source on an SoC.
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It is mandantory for ARMv8 implementation and widely available
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on ARMv7 systems.
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config ARM_SMCCC
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bool "Support for ARM SMC Calling Convention (SMCCC)"
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depends on CPU_V7 || ARM64
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@ -570,6 +580,7 @@ config ARCH_KEYSTONE
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select SUPPORT_SPL
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select SYS_THUMB_BUILD
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select CMD_POWEROFF
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select SYS_ARCH_TIMER
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imply CMD_MTDPARTS
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imply FIT
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imply CMD_SAVES
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@ -9,7 +9,7 @@ extra-y := start.o
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obj-y += cpu.o
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ifndef CONFIG_$(SPL_TPL_)TIMER
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obj-y += generic_timer.o
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obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
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endif
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obj-y += cache_v8.o
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obj-y += exceptions.o
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@ -9,6 +9,7 @@ choice
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config TARGET_MX7ULP_EVK
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bool "Support mx7ulp EVK board"
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select SYS_ARCH_TIMER
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endchoice
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@ -16,6 +16,7 @@ config TARGET_QEMU_ARM_32BIT
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depends on ARCH_QEMU
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select CPU_V7
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select ARCH_SUPPORT_PSCI
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select SYS_ARCH_TIMER
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config TARGET_QEMU_ARM_64BIT
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bool "Support qemu_arm64"
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@ -27,6 +27,7 @@ config TARGET_STM32MP1
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select CPU_V7
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select PINCTRL_STM32
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select STM32_RESET
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select SYS_ARCH_TIMER
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select SYSRESET_SYSCON
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help
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target STMicroelectronics SOC STM32MP1 family
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@ -46,7 +46,6 @@
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/* Using ULP WDOG for reset */
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#define WDOG_BASE_ADDR WDG1_RBASE
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#define CONFIG_SYS_ARCH_TIMER
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#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
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#define CONFIG_INITRD_TAG
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@ -20,7 +20,6 @@
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#define CONFIG_SYS_MALLOC_LEN SZ_16M
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/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
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#define CONFIG_SYS_ARCH_TIMER
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#define CONFIG_SYS_HZ 1000
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/* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */
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@ -17,7 +17,6 @@
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* Number of clock ticks in 1 sec
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*/
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_ARCH_TIMER
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/*
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* malloc() pool size
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@ -17,7 +17,6 @@
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/* SoC Configuration */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_SYS_ARCH_TIMER
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#define CONFIG_SPL_TARGET "u-boot-spi.gph"
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#define CONFIG_SYS_DCACHE_OFF
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@ -2074,7 +2074,6 @@ CONFIG_SYS_APP1_BASE
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CONFIG_SYS_APP1_SIZE
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CONFIG_SYS_APP2_BASE
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CONFIG_SYS_APP2_SIZE
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CONFIG_SYS_ARCH_TIMER
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CONFIG_SYS_ARM_CACHE_WRITETHROUGH
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CONFIG_SYS_AT91_CPU_NAME
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CONFIG_SYS_AT91_MAIN_CLOCK
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