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ppc4xx: Add initial Zeus (PPC405EP) board support

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2007-08-14 14:44:41 +02:00
parent c5a172a5fd
commit 779e975117
16 changed files with 1344 additions and 44 deletions
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27
cpu/ppc4xx/sdram.c
View File

@@ -187,14 +187,14 @@ void sdram_init(void)
/*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
mtsdram(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
mtsdram0(mem_mb0cf, mb0cf[i].reg);
mtsdram0(mem_sdtr1, sdtr1);
mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
mtsdram(mem_mb0cf, mb0cf[i].reg);
mtsdram(mem_sdtr1, sdtr1);
mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
@@ -203,7 +203,7 @@ void sdram_init(void)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram0(mem_mcopt1, 0x80800000);
mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
@@ -215,10 +215,21 @@ void sdram_init(void)
#ifdef CONFIG_SDRAM_BANK1
u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
mtsdram0(mem_mcopt1, 0x00000000);
mtsdram0(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
mtsdram0(mem_mcopt1, 0x80800000);
mtsdram(mem_mcopt1, 0x00000000);
mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
/*
* Check if 2nd bank is really available.
* If the size not equal to the size of the first
* bank, then disable the 2nd bank completely.
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
mb0cf[i].size) {
mtsdram(mem_mb1cf, 0);
mtsdram(mem_mcopt1, 0);
}
#endif
return;
}

2
cpu/ppc4xx/sdram.h
View File

@@ -29,8 +29,6 @@
#include <config.h>
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
#define ONE_BILLION 1000000000
struct sdram_conf_s {

48
cpu/ppc4xx/start.S
View File

@@ -1869,38 +1869,7 @@ ppc405ep_init:
ori r3,r3,CFG_EBC_PB4CR@l
mtdcr ebccfgd,r3
#endif
#ifdef CONFIG_TAIHU
mfdcr r4, CPC0_BOOT
andi. r5, r4, CPC0_BOOT_SEP@l
bne strap_0 /* serial eeprom present */
#endif
#ifndef CFG_CPC0_PCI
li r3,CPC0_PCI_HOST_CFG_EN
#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
! Check FPGA for PCI internal/external arbitration
! If board is set to internal arbitration, update cpc0_pci
!-----------------------------------------------------------------------
*/
addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
ori r5,r5,FPGA_REG1@l
lbz r5,0x0(r5) /* read to get PCI arb selection */
andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
beq ..pci_cfg_set /* if not set, then bypass reg write*/
#endif
ori r3,r3,CPC0_PCI_ARBIT_EN
#ifdef CONFIG_TAIHU
ori r3,r3,CPC0_PCI_SPE
#endif
#else /* CFG_CPC0_PCI */
li r3,CFG_CPC0_PCI
#endif /* CFG_CPC0_PCI */
..pci_cfg_set:
mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
strap_0:
/*
!-----------------------------------------------------------------------
! Check to see if chip is in bypass mode.
@@ -1966,6 +1935,21 @@ strap_0:
bne _pci_66mhz
#endif /* CONFIG_TAIHU */
#if defined(CONFIG_ZEUS)
mfdcr r4, CPC0_BOOT
andi. r5, r4, CPC0_BOOT_SEP@l
bne strap_1 /* serial eeprom present */
lis r3,0x0000
addi r3,r3,0x3030
lis r4,0x8042
addi r4,r4,0x223e
b 1f
strap_1:
mfdcr r3, CPC0_PLLMR0
mfdcr r4, CPC0_PLLMR1
b 1f
#endif
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
@@ -1982,9 +1966,9 @@ _pci_66mhz:
strap_1:
mfdcr r3, CPC0_PLLMR0
mfdcr r4, CPC0_PLLMR1
1:
#endif /* CONFIG_TAIHU */
1:
b pll_write /* Write the CPC0_PLLMR with new value */
pll_done: