board_f: Drop setup_dram_config() wrapper

By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>

arch/arm/cpu/arm926ejs/armada100/dram.c

@@ -108,7 +108,9 @@ int dram_init(void)
  * If this function is not defined here,
  * board.c alters dram bank zero configuration defined above.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	dram_init();
+
+	return 0;
 }

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -663,7 +663,7 @@ phys_size_t get_effective_memsize(void)
 	return ea_size;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 	phys_size_t dp_ddr_size;
@@ -772,6 +772,8 @@ void dram_init_banksize(void)
 		}
 	}
 #endif
+
+	return 0;
 }
 
 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)

arch/arm/include/asm/u-boot-arm.h

@@ -36,7 +36,7 @@ int	arch_early_init_r(void);
 
 /* board/.../... */
 int	board_init(void);
-void	dram_init_banksize (void);
+int dram_init_banksize(void);
 void	board_quiesce_devices(void);
 
 /* cpu/.../interrupt.c */

arch/arm/mach-davinci/misc.c

@@ -28,10 +28,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 #endif
 

arch/arm/mach-meson/board.c

@@ -34,11 +34,13 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/* Reserve first 16 MiB of RAM for firmware */
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
 	gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)

arch/arm/mach-mvebu/arm64-common.c

@@ -82,7 +82,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	const void *fdt = gd->fdt_blob;
 	const fdt32_t *val;
@@ -90,13 +90,13 @@ void dram_init_banksize(void)
 
 	val = get_memory_reg_prop(fdt, &len);
 	if (len < 0)
-		return;
+		return -ENXIO;
 
 	ac = fdt_address_cells(fdt, 0);
 	sc = fdt_size_cells(fdt, 0);
 	if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
 		printf("invalid address/size cells\n");
-		return;
+		return -ENXIO;
 	}
 
 	cells = ac + sc;
@@ -114,6 +114,8 @@ void dram_init_banksize(void)
 		      i, (unsigned long)gd->bd->bi_dram[i].start,
 		      (unsigned long)gd->bd->bi_dram[i].size);
 	}
+
+	return 0;
 }
 
 int arch_cpu_init(void)

arch/arm/mach-mvebu/dram.c

@@ -273,7 +273,7 @@ int dram_init(void)
  * If this function is not defined here,
  * board.c alters dram bank zero configuration defined above.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	u64 size = 0;
 	int i;
@@ -287,6 +287,8 @@ void dram_init_banksize(void)
 		if (size > SDRAM_SIZE_MAX)
 			mvebu_sdram_bs_set(i, 0x40000000);
 	}
+
+	return 0;
 }
 
 #if defined(CONFIG_ARCH_MVEBU)

arch/arm/mach-omap2/am33xx/emif4.c

@@ -32,10 +32,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 

arch/arm/mach-omap2/omap3/emif4.c

@@ -142,7 +142,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	unsigned int size0 = 0, size1 = 0;
 
@@ -153,6 +153,8 @@ void dram_init_banksize (void)
 	gd->bd->bi_dram[0].size = size0;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
 }
 
 /*

arch/arm/mach-omap2/omap3/sdrc.c

@@ -216,7 +216,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	unsigned int size0 = 0, size1 = 0;
 
@@ -227,6 +227,8 @@ void dram_init_banksize (void)
 	gd->bd->bi_dram[0].size = size0;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
 }
 
 /*

arch/arm/mach-orion5x/dram.c

@@ -42,7 +42,7 @@ int dram_init (void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	int i;
 
@@ -52,4 +52,6 @@ void dram_init_banksize (void)
 			(long *) (gd->bd->bi_dram[i].start),
 			CONFIG_MAX_RAM_BANK_SIZE);
 	}
+
+	return 0;
 }

arch/arm/mach-tegra/board2.c

@@ -315,7 +315,7 @@ static ulong usable_ram_size_below_4g(void)
  * start address of that bank cannot be represented in the 32-bit .size
  * field.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
@@ -334,6 +334,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].start = 0;
 		gd->bd->bi_dram[1].size = 0;
 	}
+
+	return 0;
 }
 
 /*

arch/arm/mach-tegra/tegra186/nvtboot_mem.c

@@ -72,7 +72,7 @@ int dram_init(void)
 
 extern unsigned long nvtboot_boot_x0;
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i;
 
@@ -80,6 +80,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = ram_banks[i].start;
 		gd->bd->bi_dram[i].size = ram_banks[i].size;
 	}
+
+	return 0;
 }
 
 ulong board_get_usable_ram_top(ulong total_size)

arch/arm/mach-uniphier/dram_init.c

@@ -232,7 +232,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	struct uniphier_dram_map dram_map[3] = {};
 	int i;
@@ -246,6 +246,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = dram_map[i].base;
 		gd->bd->bi_dram[i].size = dram_map[i].size;
 	}
+
+	return 0;
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP

arch/x86/cpu/broadwell/sdram.c

@@ -28,9 +28,11 @@ ulong board_get_usable_ram_top(ulong total_size)
 	return mrc_common_board_get_usable_ram_top(total_size);
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	mrc_common_dram_init_banksize();
+
+	return 0;
 }
 
 void broadwell_fill_pei_data(struct pei_data *pei_data)

arch/x86/cpu/coreboot/sdram.c

@@ -104,7 +104,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i, j;
 
@@ -121,4 +121,6 @@ void dram_init_banksize(void)
 			}
 		}
 	}
+
+	return 0;
 }

arch/x86/cpu/efi/sdram.c

@@ -22,8 +22,10 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = efi_get_ram_base();
 	gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE;
+
+	return 0;
 }

arch/x86/cpu/ivybridge/sdram.c

@@ -46,9 +46,11 @@ ulong board_get_usable_ram_top(ulong total_size)
 	return mrc_common_board_get_usable_ram_top(total_size);
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	mrc_common_dram_init_banksize();
+
+	return 0;
 }
 
 static int read_seed_from_cmos(struct pei_data *pei_data)

arch/x86/cpu/qemu/dram.c

@@ -26,10 +26,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*

arch/x86/cpu/quark/dram.c

@@ -162,10 +162,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*

arch/x86/include/asm/u-boot-x86.h

@@ -41,7 +41,7 @@ void x86_disable_caches(void);
 int x86_init_cache(void);
 void reset_cpu(ulong addr);
 ulong board_get_usable_ram_top(ulong total_size);
-void dram_init_banksize(void);
+int dram_init_banksize(void);
 int default_print_cpuinfo(void);
 
 /* Set up a UART which can be used with printch(), printhex8(), etc. */

arch/x86/lib/efi/efi.c

@@ -92,7 +92,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	struct efi_mem_desc *desc, *end;
 	struct efi_entry_memmap *map;
@@ -103,7 +103,7 @@ void dram_init_banksize(void)
 	if (ret) {
 		/* We should have stopped in dram_init(), something is wrong */
 		debug("%s: Missing memory map\n", __func__);
-		return;
+		return -ENXIO;
 	}
 	end = (struct efi_mem_desc *)((ulong)map + size);
 	desc = map->desc;
@@ -123,6 +123,8 @@ void dram_init_banksize(void)
 			EFI_PAGE_SHIFT;
 		num_banks++;
 	}
+
+	return 0;
 }
 
 int checkcpu(void)

arch/x86/lib/fsp/fsp_dram.c

@@ -41,10 +41,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*