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arm: tegra: Fix the CPU complex reset masks

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The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swrren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Alban Bedel 2013-11-20 17:42:46 +01:00 committed by Tom Warren
parent 8f38038193
commit 766afc3dff
1 changed files with 3 additions and 3 deletions
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6
arch/arm/include/asm/arch-tegra/clock.h
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@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable);
enum crc_reset_id {
/* Things we can hold in reset for each CPU */
crc_rst_cpu = 1,
crc_rst_de = 1 << 2, /* What is de? */
crc_rst_watchdog = 1 << 3,
crc_rst_debug = 1 << 4,
crc_rst_de = 1 << 4, /* What is de? */
crc_rst_watchdog = 1 << 8,
crc_rst_debug = 1 << 12,
};
/**