PXA: Remove "delta" board
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Marek Vasut
parent
9b3d167fde
commit
75e203584a
@ -1,52 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := delta.o nand.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1 +0,0 @@
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CONFIG_SYS_TEXT_BASE = 0x83008000
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@ -1,378 +0,0 @@
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/*
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* (C) Copyright 2006
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* DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <da9030.h>
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#include <malloc.h>
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#include <command.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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static void init_DA9030(void);
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static void keys_init(void);
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static void get_pressed_keys(uchar *s);
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static uchar *key_match(uchar *kbd_data);
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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/* arch number of Lubbock-Board mk@tbd: fix this! */
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gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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return 0;
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}
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int board_late_init(void)
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{
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#ifdef DELTA_CHECK_KEYBD
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uchar kbd_data[KEYBD_DATALEN];
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char keybd_env[2 * KEYBD_DATALEN + 1];
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char *str;
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int i;
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#endif /* DELTA_CHECK_KEYBD */
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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#ifdef DELTA_CHECK_KEYBD
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keys_init();
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memset(kbd_data, '\0', KEYBD_DATALEN);
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/* check for pressed keys and setup keybd_env */
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get_pressed_keys(kbd_data);
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for (i = 0; i < KEYBD_DATALEN; ++i) {
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sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
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}
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setenv ("keybd", keybd_env);
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str = strdup ((char *)key_match (kbd_data)); /* decode keys */
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# ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
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setenv ("preboot", str); /* set or delete definition */
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# endif /* CONFIG_PREBOOT */
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if (str != NULL) {
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free (str);
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}
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#endif /* DELTA_CHECK_KEYBD */
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init_DA9030();
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return 0;
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}
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/*
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* Magic Key Handling, mainly copied from board/lwmon/lwmon.c
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*/
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#ifdef DELTA_CHECK_KEYBD
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static uchar kbd_magic_prefix[] = "key_magic";
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static uchar kbd_command_prefix[] = "key_cmd";
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/*
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* Get pressed keys
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* s is a buffer of size KEYBD_DATALEN-1
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*/
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static void get_pressed_keys(uchar *s)
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{
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unsigned long val;
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val = readl(GPLR3);
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if(val & (1<<31))
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*s++ = KEYBD_KP_DKIN0;
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if(val & (1<<18))
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*s++ = KEYBD_KP_DKIN1;
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if(val & (1<<29))
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*s++ = KEYBD_KP_DKIN2;
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if(val & (1<<22))
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*s++ = KEYBD_KP_DKIN5;
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}
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static void keys_init()
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{
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writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
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udelay(100);
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/* Configure GPIOs */
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writel(0xa840, GPIO127); /* KP_DKIN0 */
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writel(0xa840, GPIO114); /* KP_DKIN1 */
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writel(0xa840, GPIO125); /* KP_DKIN2 */
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writel(0xa840, GPIO118); /* KP_DKIN5 */
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/* Configure GPIOs as inputs */
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writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
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writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
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udelay(100);
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}
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static int compare_magic (uchar *kbd_data, uchar *str)
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{
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/* uchar compare[KEYBD_DATALEN-1]; */
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uchar compare[KEYBD_DATALEN];
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char *nxt;
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int i;
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/* Don't include modifier byte */
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/* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */
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memcpy (compare, kbd_data, KEYBD_DATALEN);
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for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
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uchar c;
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int k;
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c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
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if (str == (uchar *)nxt) { /* invalid character */
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break;
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}
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/*
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* Check if this key matches the input.
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* Set matches to zero, so they match only once
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* and we can find duplicates or extra keys
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*/
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for (k = 0; k < sizeof(compare); ++k) {
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if (compare[k] == '\0') /* only non-zero entries */
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continue;
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if (c == compare[k]) { /* found matching key */
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compare[k] = '\0';
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break;
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}
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}
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if (k == sizeof(compare)) {
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return -1; /* unmatched key */
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}
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}
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/*
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* A full match leaves no keys in the `compare' array,
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*/
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for (i = 0; i < sizeof(compare); ++i) {
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if (compare[i])
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{
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return -1;
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}
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}
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return 0;
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}
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static uchar *key_match (uchar *kbd_data)
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{
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char magic[sizeof (kbd_magic_prefix) + 1];
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uchar *suffix;
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char *kbd_magic_keys;
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/*
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* The following string defines the characters that can pe appended
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* to "key_magic" to form the names of environment variables that
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* hold "magic" key codes, i. e. such key codes that can cause
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* pre-boot actions. If the string is empty (""), then only
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* "key_magic" is checked (old behaviour); the string "125" causes
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* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
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*/
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if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
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kbd_magic_keys = "";
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/* loop over all magic keys;
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* use '\0' suffix in case of empty string
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*/
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for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
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sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
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#if 0
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printf ("### Check magic \"%s\"\n", magic);
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#endif
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if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
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char cmd_name[sizeof (kbd_command_prefix) + 1];
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char *cmd;
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sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
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cmd = getenv (cmd_name);
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#if 0
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printf ("### Set PREBOOT to $(%s): \"%s\"\n",
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cmd_name, cmd ? cmd : "<<NULL>>");
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#endif
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*kbd_data = *suffix;
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return ((uchar *)cmd);
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}
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}
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#if 0
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printf ("### Delete PREBOOT\n");
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#endif
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*kbd_data = '\0';
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return (NULL);
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}
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int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uchar kbd_data[KEYBD_DATALEN];
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char keybd_env[2 * KEYBD_DATALEN + 1];
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int i;
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/* Read keys */
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get_pressed_keys(kbd_data);
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puts ("Keys:");
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for (i = 0; i < KEYBD_DATALEN; ++i) {
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sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
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printf (" %02x", kbd_data[i]);
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}
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putc ('\n');
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setenv ("keybd", keybd_env);
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return 0;
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}
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U_BOOT_CMD(
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kbd, 1, 1, do_kbd,
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"read keyboard status",
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""
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);
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#endif /* DELTA_CHECK_KEYBD */
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
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return 0;
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}
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void i2c_init_board()
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{
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writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
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/* setup I2C GPIO's */
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writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */
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writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */
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}
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/* initialize the DA9030 Power Controller */
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static void init_DA9030()
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{
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uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
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writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
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udelay(100);
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/* Rising Edge on EXTON to reset DA9030 */
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writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */
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writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */
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writel((1<<17), GSDR0);
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writel((1<<17), GPCR0); /* drive GPIO17 low */
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writel((1<<17), GPSR0); /* drive GPIO17 high */
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#if CONFIG_SYS_DA9030_EXTON_DELAY
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udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */
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#endif
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writel((1<<17), GPCR0); /* drive GPIO17 low */
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/* reset the watchdog and go active (0xec) */
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val = (SYS_CONTROL_A_HWRES_ENABLE |
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(0x6<<4) |
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SYS_CONTROL_A_WDOG_ACTION |
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SYS_CONTROL_A_WATCHDOG);
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if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) {
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printf("Error accessing DA9030 via i2c.\n");
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return;
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}
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val = 0x80;
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if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) {
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printf("Error accessing DA9030 via i2c.\n");
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return;
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}
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i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
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i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */
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i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */
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i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */
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i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */
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i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */
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i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */
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i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
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i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */
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i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */
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i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */
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i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */
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i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
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i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */
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i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
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i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
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i2c_reg_write(addr, USBPUMP, 0xc1); /* start pump, ignore HW signals */
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val = i2c_reg_read(addr, STATUS);
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if(val & STATUS_CHDET)
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printf("Charger detected, turning on LED.\n");
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else {
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printf("No charger detetected.\n");
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/* undervoltage? print error and power down */
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}
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}
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#if 0
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/* reset the DA9030 watchdog */
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void hw_watchdog_reset(void)
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{
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uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
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val = i2c_reg_read(addr, SYS_CONTROL_A);
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val |= SYS_CONTROL_A_WATCHDOG;
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i2c_reg_write(addr, SYS_CONTROL_A, val);
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}
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#endif
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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return rc;
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}
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#endif
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@ -1,146 +0,0 @@
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/*
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* (C) Copyright 2006 DENX Software Engineering
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||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
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#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
|
||||
|
||||
.macro wait time
|
||||
ldr r2, =OSCR
|
||||
mov r3, #0
|
||||
str r3, [r2]
|
||||
0:
|
||||
ldr r3, [r2]
|
||||
cmp r3, \time
|
||||
bls 0b
|
||||
.endm
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
/* Set up GPIO pins first */
|
||||
mov r10, lr
|
||||
|
||||
/* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
|
||||
ldr r0, =GPIO97
|
||||
ldr r1, =0x801
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPIO98
|
||||
ldr r1, =0x801
|
||||
str r1, [r0]
|
||||
|
||||
/* tebrandt - ASCR, clear the RDH bit */
|
||||
ldr r0, =ASCR
|
||||
ldr r1, [r0]
|
||||
bic r1, r1, #0x80000000
|
||||
str r1, [r0]
|
||||
|
||||
mem_init:
|
||||
/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
|
||||
ldr r0, =ACCR
|
||||
ldr r1, [r0]
|
||||
orr r1, r1, #0x3000
|
||||
str r1, [r0]
|
||||
ldr r1, [r0]
|
||||
|
||||
/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
|
||||
ldr r0, =MDCNFG
|
||||
ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
|
||||
/* ldr r1, =0x80000403 */
|
||||
str r1, [r0]
|
||||
ldr r1, [r0] /* delay until written */
|
||||
|
||||
/* 3. wait nop power up waiting period (200ms)
|
||||
* optimization: Steps 4+6 can be done during this
|
||||
*/
|
||||
wait #0x300
|
||||
|
||||
/* 4. Perform an initial Rcomp-calibration cycle */
|
||||
ldr r0, =RCOMP
|
||||
ldr r1, =0x80000000
|
||||
str r1, [r0]
|
||||
ldr r1, [r0] /* delay until written */
|
||||
/* missing: program for automatic rcomp evaluation cycles */
|
||||
|
||||
/* 5. DDR DRAM strobe delay calibration */
|
||||
ldr r0, =DDR_HCAL
|
||||
ldr r1, =0x88000007
|
||||
str r1, [r0]
|
||||
wait #5
|
||||
ldr r1, [r0] /* delay until written */
|
||||
|
||||
/* Set MDMRS */
|
||||
ldr r0, =MDMRS
|
||||
ldr r1, =0x60000033
|
||||
str r1, [r0]
|
||||
wait #300
|
||||
|
||||
/* Configure MDREFR */
|
||||
ldr r0, =MDREFR
|
||||
ldr r1, =0x00000006
|
||||
str r1, [r0]
|
||||
ldr r1, [r0]
|
||||
|
||||
/* Enable the dynamic memory controller */
|
||||
ldr r0, =MDCNFG
|
||||
ldr r1, [r0]
|
||||
orr r1, r1, #MDCNFG_DMCEN
|
||||
str r1, [r0]
|
||||
|
||||
#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
|
||||
/* scrub/init SDRAM if enabled/present */
|
||||
ldr r8, =CONFIG_SYS_DRAM_BASE /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
|
||||
ldr r9, =CONFIG_SYS_DRAM_SIZE /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
|
||||
mov r0, #0 /* scrub with 0x0000:0000 */
|
||||
mov r1, #0
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
mov r4, #0
|
||||
mov r5, #0
|
||||
mov r6, #0
|
||||
mov r7, #0
|
||||
10: /* fastScrubLoop */
|
||||
subs r9, r9, #32 /* 8 words/line */
|
||||
stmia r8!, {r0-r7}
|
||||
beq 15f
|
||||
b 10b
|
||||
#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
|
||||
|
||||
15:
|
||||
/* Mask all interrupts */
|
||||
mov r1, #0
|
||||
mcr p6, 0, r1, c1, c0, 0 @ ICMR
|
||||
|
||||
/* Disable software and data breakpoints */
|
||||
mov r0, #0
|
||||
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
|
||||
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
|
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */
|
||||
|
||||
/* Enable all debug functionality */
|
||||
mov r0,#0x80000000
|
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */
|
||||
|
||||
endlowlevel_init:
|
||||
mov pc, lr
|
||||
@ -1,558 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2006 DENX Software Engineering
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
|
||||
#include <nand.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_SYS_DFC_DEBUG1
|
||||
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
|
||||
#else
|
||||
# define DFC_DEBUG1(fmt, args...)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_DFC_DEBUG2
|
||||
# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
|
||||
#else
|
||||
# define DFC_DEBUG2(fmt, args...)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_DFC_DEBUG3
|
||||
# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
|
||||
#else
|
||||
# define DFC_DEBUG3(fmt, args...)
|
||||
#endif
|
||||
|
||||
/* These really don't belong here, as they are specific to the NAND Model */
|
||||
static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
|
||||
|
||||
static struct nand_bbt_descr delta_bbt_descr = {
|
||||
.options = 0,
|
||||
.offs = 0,
|
||||
.len = 2,
|
||||
.pattern = scan_ff_pattern
|
||||
};
|
||||
|
||||
static struct nand_ecclayout delta_oob = {
|
||||
.eccbytes = 6,
|
||||
.eccpos = {2, 3, 4, 5, 6, 7},
|
||||
.oobfree = { {8, 2}, {12, 4} }
|
||||
};
|
||||
|
||||
/*
|
||||
* not required for Monahans DFC
|
||||
*/
|
||||
static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* read device ready pin */
|
||||
static int dfc_device_ready(struct mtd_info *mtdinfo)
|
||||
{
|
||||
if(NDSR & NDSR_RDY)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Write buf to the DFC Controller Data Buffer
|
||||
*/
|
||||
static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
unsigned long bytes_multi = len & 0xfffffffc;
|
||||
unsigned long rest = len & 0x3;
|
||||
unsigned long *long_buf;
|
||||
int i;
|
||||
|
||||
DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
|
||||
if(bytes_multi) {
|
||||
for(i=0; i<bytes_multi; i+=4) {
|
||||
long_buf = (unsigned long*) &buf[i];
|
||||
writel(*long_buf, NDDB);
|
||||
}
|
||||
}
|
||||
if(rest) {
|
||||
printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
|
||||
{
|
||||
int i=0, j;
|
||||
|
||||
/* we have to be carefull not to overflow the buffer if len is
|
||||
* not a multiple of 4 */
|
||||
unsigned long bytes_multi = len & 0xfffffffc;
|
||||
unsigned long rest = len & 0x3;
|
||||
unsigned long *long_buf;
|
||||
|
||||
DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
|
||||
/* if there are any, first copy multiple of 4 bytes */
|
||||
if(bytes_multi) {
|
||||
for(i=0; i<bytes_multi; i+=4) {
|
||||
long_buf = (unsigned long*) &buf[i];
|
||||
*long_buf = readl(NDDB);
|
||||
}
|
||||
}
|
||||
|
||||
/* ...then the rest */
|
||||
if(rest) {
|
||||
unsigned long rest_data = NDDB;
|
||||
for(j=0;j<rest; j++)
|
||||
buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* read a word. Not implemented as not used in NAND code.
|
||||
*/
|
||||
static u16 dfc_read_word(struct mtd_info *mtd)
|
||||
{
|
||||
printf("dfc_read_word: UNIMPLEMENTED.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* global var, too bad: mk@tbd: move to ->priv pointer */
|
||||
static unsigned long read_buf = 0;
|
||||
static int bytes_read = -1;
|
||||
|
||||
/*
|
||||
* read a byte from NDDB Because we can only read 4 bytes from NDDB at
|
||||
* a time, we buffer the remaining bytes. The buffer is reset when a
|
||||
* new command is sent to the chip.
|
||||
*
|
||||
* WARNING:
|
||||
* This function is currently only used to read status and id
|
||||
* bytes. For these commands always 8 bytes need to be read from
|
||||
* NDDB. So we read and discard these bytes right now. In case this
|
||||
* function is used for anything else in the future, we must check
|
||||
* what was the last command issued and read the appropriate amount of
|
||||
* bytes respectively.
|
||||
*/
|
||||
static u_char dfc_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
unsigned char byte;
|
||||
unsigned long dummy;
|
||||
|
||||
if(bytes_read < 0) {
|
||||
read_buf = readl(NDDB);
|
||||
dummy = readl(NDDB);
|
||||
bytes_read = 0;
|
||||
}
|
||||
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
|
||||
if(bytes_read >= 4)
|
||||
bytes_read = -1;
|
||||
|
||||
DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
|
||||
return byte;
|
||||
}
|
||||
|
||||
/* calculate delta between OSCR values start and now */
|
||||
static unsigned long get_delta(unsigned long start)
|
||||
{
|
||||
unsigned long cur = readl(OSCR);
|
||||
|
||||
if(cur < start) /* OSCR overflowed */
|
||||
return (cur + (start^0xffffffff));
|
||||
else
|
||||
return (cur - start);
|
||||
}
|
||||
|
||||
/* delay function, this doesn't belong here */
|
||||
static void wait_us(unsigned long us)
|
||||
{
|
||||
unsigned long start = readl(OSCR);
|
||||
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
|
||||
|
||||
while (get_delta(start) < us) {
|
||||
/* do nothing */
|
||||
}
|
||||
}
|
||||
|
||||
static void dfc_clear_nddb(void)
|
||||
{
|
||||
writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
|
||||
wait_us(CONFIG_SYS_NAND_OTHER_TO);
|
||||
}
|
||||
|
||||
/* wait_event with timeout */
|
||||
static unsigned long dfc_wait_event(unsigned long event)
|
||||
{
|
||||
unsigned long ndsr, timeout, start = readl(OSCR);
|
||||
|
||||
if(!event)
|
||||
return 0xff000000;
|
||||
else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
|
||||
timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
|
||||
* OSCR_CLK_FREQ, 1000);
|
||||
else
|
||||
timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
|
||||
* OSCR_CLK_FREQ, 1000);
|
||||
|
||||
while(1) {
|
||||
ndsr = readl(NDSR);
|
||||
if(ndsr & event) {
|
||||
writel(readl(NDSR) | event, NDSR);
|
||||
break;
|
||||
}
|
||||
if(get_delta(start) > timeout) {
|
||||
DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
|
||||
return 0xff000000;
|
||||
}
|
||||
|
||||
}
|
||||
return ndsr;
|
||||
}
|
||||
|
||||
/* we don't always wan't to do this */
|
||||
static void dfc_new_cmd(void)
|
||||
{
|
||||
int retry = 0;
|
||||
unsigned long status;
|
||||
|
||||
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
|
||||
/* Clear NDSR */
|
||||
writel(0xfff, NDSR);
|
||||
|
||||
/* set NDCR[NDRUN] */
|
||||
if (!(readl(NDCR) & NDCR_ND_RUN))
|
||||
writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
|
||||
|
||||
status = dfc_wait_event(NDSR_WRCMDREQ);
|
||||
|
||||
if(status & NDSR_WRCMDREQ)
|
||||
return;
|
||||
|
||||
DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
|
||||
dfc_clear_nddb();
|
||||
}
|
||||
DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
|
||||
}
|
||||
|
||||
/* this function is called after Programm and Erase Operations to
|
||||
* check for success or failure */
|
||||
static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
|
||||
{
|
||||
unsigned long ndsr=0, event=0;
|
||||
int state = this->state;
|
||||
|
||||
if(state == FL_WRITING) {
|
||||
event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
|
||||
} else if(state == FL_ERASING) {
|
||||
event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
|
||||
}
|
||||
|
||||
ndsr = dfc_wait_event(event);
|
||||
|
||||
if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
|
||||
return(0x1); /* Status Read error */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* cmdfunc send commands to the DFC */
|
||||
static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
|
||||
int column, int page_addr)
|
||||
{
|
||||
/* register struct nand_chip *this = mtd->priv; */
|
||||
unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
|
||||
|
||||
/* clear the ugly byte read buffer */
|
||||
bytes_read = -1;
|
||||
read_buf = 0;
|
||||
|
||||
switch (command) {
|
||||
case NAND_CMD_READ0:
|
||||
DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
|
||||
dfc_new_cmd();
|
||||
ndcb0 = (NAND_CMD_READ0 | (4<<16));
|
||||
column >>= 1; /* adjust for 16 bit bus */
|
||||
ndcb1 = (((column>>1) & 0xff) |
|
||||
((page_addr<<8) & 0xff00) |
|
||||
((page_addr<<8) & 0xff0000) |
|
||||
((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
|
||||
event = NDSR_RDDREQ;
|
||||
goto write_cmd;
|
||||
case NAND_CMD_READ1:
|
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
|
||||
goto end;
|
||||
case NAND_CMD_READOOB:
|
||||
DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
|
||||
goto end;
|
||||
case NAND_CMD_READID:
|
||||
dfc_new_cmd();
|
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
|
||||
ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
|
||||
event = NDSR_RDDREQ;
|
||||
goto write_cmd;
|
||||
case NAND_CMD_PAGEPROG:
|
||||
/* sent as a multicommand in NAND_CMD_SEQIN */
|
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
|
||||
goto end;
|
||||
case NAND_CMD_ERASE1:
|
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
|
||||
dfc_new_cmd();
|
||||
ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
|
||||
ndcb1 = (page_addr & 0x00ffffff);
|
||||
goto write_cmd;
|
||||
case NAND_CMD_ERASE2:
|
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
|
||||
goto end;
|
||||
case NAND_CMD_SEQIN:
|
||||
/* send PAGE_PROG command(0x1080) */
|
||||
dfc_new_cmd();
|
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
|
||||
ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
|
||||
column >>= 1; /* adjust for 16 bit bus */
|
||||
ndcb1 = (((column>>1) & 0xff) |
|
||||
((page_addr<<8) & 0xff00) |
|
||||
((page_addr<<8) & 0xff0000) |
|
||||
((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
|
||||
event = NDSR_WRDREQ;
|
||||
goto write_cmd;
|
||||
case NAND_CMD_STATUS:
|
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
|
||||
dfc_new_cmd();
|
||||
ndcb0 = NAND_CMD_STATUS | (4<<21);
|
||||
event = NDSR_RDDREQ;
|
||||
goto write_cmd;
|
||||
case NAND_CMD_RESET:
|
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
|
||||
ndcb0 = NAND_CMD_RESET | (5<<21);
|
||||
event = NDSR_CS0_CMDD;
|
||||
goto write_cmd;
|
||||
default:
|
||||
printk("dfc_cmdfunc: error, unsupported command.\n");
|
||||
goto end;
|
||||
}
|
||||
|
||||
write_cmd:
|
||||
writel(ndcb0, NDCB0);
|
||||
writel(ndcb1, NDCB0);
|
||||
writel(ndcb2, NDCB0);
|
||||
|
||||
/* wait_event: */
|
||||
dfc_wait_event(event);
|
||||
end:
|
||||
return;
|
||||
}
|
||||
|
||||
static void dfc_gpio_init(void)
|
||||
{
|
||||
DFC_DEBUG2("Setting up DFC GPIO's.\n");
|
||||
|
||||
/* no idea what is done here, see zylonite.c */
|
||||
writel(0x1, GPIO4);
|
||||
|
||||
writel(0x00000001, DF_ALE_nWE1);
|
||||
writel(0x00000001, DF_ALE_nWE2);
|
||||
writel(0x00000001, DF_nCS0);
|
||||
writel(0x00000001, DF_nCS1);
|
||||
writel(0x00000001, DF_nWE);
|
||||
writel(0x00000001, DF_nRE);
|
||||
writel(0x00000001, DF_IO0);
|
||||
writel(0x00000001, DF_IO8);
|
||||
writel(0x00000001, DF_IO1);
|
||||
writel(0x00000001, DF_IO9);
|
||||
writel(0x00000001, DF_IO2);
|
||||
writel(0x00000001, DF_IO10);
|
||||
writel(0x00000001, DF_IO3);
|
||||
writel(0x00000001, DF_IO11);
|
||||
writel(0x00000001, DF_IO4);
|
||||
writel(0x00000001, DF_IO12);
|
||||
writel(0x00000001, DF_IO5);
|
||||
writel(0x00000001, DF_IO13);
|
||||
writel(0x00000001, DF_IO6);
|
||||
writel(0x00000001, DF_IO14);
|
||||
writel(0x00000001, DF_IO7);
|
||||
writel(0x00000001, DF_IO15);
|
||||
|
||||
writel(0x1901, DF_nWE);
|
||||
writel(0x1901, DF_nRE);
|
||||
writel(0x1900, DF_CLE_nOE);
|
||||
writel(0x1901, DF_ALE_nWE1);
|
||||
writel(0x1900, DF_INT_RnB);
|
||||
}
|
||||
|
||||
/*
|
||||
* Board-specific NAND initialization. The following members of the
|
||||
* argument are board-specific (per include/linux/mtd/nand_new.h):
|
||||
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
|
||||
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
|
||||
* - hwcontrol: hardwarespecific function for accesing control-lines
|
||||
* - dev_ready: hardwarespecific function for accesing device ready/busy line
|
||||
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
|
||||
* only be provided if a hardware ECC is available
|
||||
* - ecc.mode: mode of ecc, see defines
|
||||
* - chip_delay: chip dependent delay for transfering data from array to
|
||||
* read regs (tR)
|
||||
* - options: various chip options. They can partly be set to inform
|
||||
* nand_scan about special functionality. See the defines for further
|
||||
* explanation
|
||||
* Members with a "?" were not set in the merged testing-NAND branch,
|
||||
* so they are not set here either.
|
||||
*/
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
|
||||
|
||||
/* set up GPIO Control Registers */
|
||||
dfc_gpio_init();
|
||||
|
||||
/* turn on the NAND Controller Clock (104 MHz @ D0) */
|
||||
writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
|
||||
|
||||
#undef CONFIG_SYS_TIMING_TIGHT
|
||||
#ifndef CONFIG_SYS_TIMING_TIGHT
|
||||
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tCH);
|
||||
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tCS);
|
||||
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tWH);
|
||||
tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tWP);
|
||||
tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tRH);
|
||||
tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tRP);
|
||||
tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tR);
|
||||
tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tWHR);
|
||||
tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tAR);
|
||||
#else /* this is the tight timing */
|
||||
|
||||
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
|
||||
DFC_MAX_tCH);
|
||||
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
|
||||
DFC_MAX_tCS);
|
||||
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
|
||||
DFC_MAX_tWH);
|
||||
tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
|
||||
DFC_MAX_tWP);
|
||||
tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
|
||||
DFC_MAX_tRH);
|
||||
tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
|
||||
DFC_MAX_tRP);
|
||||
tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
|
||||
DFC_MAX_tR);
|
||||
tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
|
||||
DFC_MAX_tWHR);
|
||||
tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
|
||||
DFC_MAX_tAR);
|
||||
#endif /* CONFIG_SYS_TIMING_TIGHT */
|
||||
|
||||
|
||||
DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
|
||||
|
||||
/* tRP value is split in the register */
|
||||
if(tRP & (1 << 4)) {
|
||||
tRP_high = 1;
|
||||
tRP &= ~(1 << 4);
|
||||
} else {
|
||||
tRP_high = 0;
|
||||
}
|
||||
|
||||
writel((tCH << 19) |
|
||||
(tCS << 16) |
|
||||
(tWH << 11) |
|
||||
(tWP << 8) |
|
||||
(tRP_high << 6) |
|
||||
(tRH << 3) |
|
||||
(tRP << 0),
|
||||
NDTR0CS0);
|
||||
|
||||
writel((tR << 16) |
|
||||
(tWHR << 4) |
|
||||
(tAR << 0),
|
||||
NDTR1CS0);
|
||||
|
||||
/* If it doesn't work (unlikely) think about:
|
||||
* - ecc enable
|
||||
* - chip select don't care
|
||||
* - read id byte count
|
||||
*
|
||||
* Intentionally enabled by not setting bits:
|
||||
* - dma (DMA_EN)
|
||||
* - page size = 512
|
||||
* - cs don't care, see if we can enable later!
|
||||
* - row address start position (after second cycle)
|
||||
* - pages per block = 32
|
||||
* - ND_RDY : clears command buffer
|
||||
*/
|
||||
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
|
||||
|
||||
writel(NDCR_SPARE_EN | /* use the spare area */
|
||||
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
|
||||
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
|
||||
(2 << 16) | /* read id count = 7 ???? mk@tbd */
|
||||
NDCR_ND_ARB_EN | /* enable bus arbiter */
|
||||
NDCR_RDYM | /* flash device ready ir masked */
|
||||
NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
|
||||
NDCR_CS1_PAGEDM |
|
||||
NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
|
||||
NDCR_CS1_CMDDM |
|
||||
NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
|
||||
NDCR_CS1_BBDM |
|
||||
NDCR_DBERRM | /* double bit error ir masked */
|
||||
NDCR_SBERRM | /* single bit error ir masked */
|
||||
NDCR_WRDREQM | /* write data request ir masked */
|
||||
NDCR_RDDREQM | /* read data request ir masked */
|
||||
NDCR_WRCMDREQM, /* write command request ir masked */
|
||||
NDCR);
|
||||
|
||||
|
||||
/* wait 10 us due to cmd buffer clear reset */
|
||||
/* wait(10); */
|
||||
|
||||
|
||||
nand->cmd_ctrl = dfc_hwcontrol;
|
||||
/* nand->dev_ready = dfc_device_ready; */
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
nand->ecc.layout = &delta_oob;
|
||||
nand->options = NAND_BUSWIDTH_16;
|
||||
nand->waitfunc = dfc_wait;
|
||||
nand->read_byte = dfc_read_byte;
|
||||
nand->read_word = dfc_read_word;
|
||||
nand->read_buf = dfc_read_buf;
|
||||
nand->write_buf = dfc_write_buf;
|
||||
|
||||
nand->cmdfunc = dfc_cmdfunc;
|
||||
nand->badblock_pattern = &delta_bbt_descr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -65,7 +65,6 @@ balloon3 arm pxa
|
||||
cerf250 arm pxa
|
||||
cradle arm pxa
|
||||
csb226 arm pxa
|
||||
delta arm pxa
|
||||
innokom arm pxa
|
||||
lubbock arm pxa
|
||||
palmld arm pxa
|
||||
|
||||
@ -1,267 +0,0 @@
|
||||
/*
|
||||
* Configuation settings for the Delta board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
|
||||
#define CONFIG_CPU_PXA320
|
||||
#define CONFIG_DELTA 1 /* Delta board */
|
||||
|
||||
/* #define CONFIG_LCD 1 */
|
||||
#ifdef CONFIG_LCD
|
||||
#define CONFIG_SHARP_LM8V31
|
||||
#endif
|
||||
#define BOARD_LATE_INIT 1
|
||||
|
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
/* we will never enable dcache, because we have to setup MMU first */
|
||||
#define CONFIG_SYS_NO_DCACHE
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#undef TURN_ON_ETHERNET
|
||||
#ifdef TURN_ON_ETHERNET
|
||||
# define CONFIG_DRIVER_SMC91111 1
|
||||
# define CONFIG_SMC91111_BASE 0x14000300
|
||||
# define CONFIG_SMC91111_EXT_PHY
|
||||
# define CONFIG_SMC_USE_32_BIT
|
||||
# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
|
||||
#endif
|
||||
|
||||
#define CONFIG_HARD_I2C 1 /* required for DA9030 access */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_SLAVE 1 /* I2C controllers address */
|
||||
#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
|
||||
#define CONFIG_SYS_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD 1
|
||||
/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
|
||||
|
||||
#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */
|
||||
#define CONFIG_PREBOOT "\0"
|
||||
|
||||
#ifdef DELTA_CHECK_KEYBD
|
||||
# define KEYBD_DATALEN 4 /* we have four keys */
|
||||
# define KEYBD_KP_DKIN0 0x1 /* vol+ */
|
||||
# define KEYBD_KP_DKIN1 0x2 /* vol- */
|
||||
# define KEYBD_KP_DKIN2 0x3 /* multi */
|
||||
# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */
|
||||
#endif /* DELTA_CHECK_KEYBD */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_PXA_SERIAL
|
||||
#define CONFIG_FFUART 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#ifdef TURN_ON_ETHERNET
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#else
|
||||
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_I2C
|
||||
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
|
||||
|
||||
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE OHCI_REGS_BASE
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
|
||||
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
|
||||
#define CONFIG_NETMASK 255.255.0.0
|
||||
#define CONFIG_IPADDR 192.168.0.21
|
||||
#define CONFIG_SERVERIP 192.168.0.250
|
||||
#define CONFIG_BOOTCOMMAND "bootm 80000"
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_TIMESTAMP
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER 1
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
|
||||
#else
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#endif
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Monahans Core Frequency */
|
||||
#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
|
||||
#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
|
||||
|
||||
|
||||
/* valid baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_PXA_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_SYS_MMC_BASE 0xF0000000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
|
||||
#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
|
||||
|
||||
#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
|
||||
#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
|
||||
|
||||
#undef CONFIG_SYS_SKIP_DRAM_SCRUB
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
|
||||
|
||||
/*
|
||||
* NAND Flash
|
||||
*/
|
||||
#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
|
||||
#undef CONFIG_SYS_NAND1_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
|
||||
/* nand timeout values */
|
||||
#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
|
||||
#define CONFIG_SYS_NAND_OTHER_TO 100
|
||||
#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
|
||||
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
|
||||
|
||||
/* NAND Timing Parameters (in ns) */
|
||||
#define NAND_TIMING_tCH 10
|
||||
#define NAND_TIMING_tCS 0
|
||||
#define NAND_TIMING_tWH 20
|
||||
#define NAND_TIMING_tWP 40
|
||||
|
||||
#define NAND_TIMING_tRH 20
|
||||
#define NAND_TIMING_tRP 40
|
||||
|
||||
#define NAND_TIMING_tR 11123
|
||||
#define NAND_TIMING_tWHR 100
|
||||
#define NAND_TIMING_tAR 10
|
||||
|
||||
/* NAND debugging */
|
||||
#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
|
||||
#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
|
||||
#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
|
||||
|
||||
#define CONFIG_MTD_DEBUG
|
||||
#define CONFIG_MTD_DEBUG_VERBOSE 1
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH 1
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_OFFSET 0x40000
|
||||
#define CONFIG_ENV_OFFSET_REDUND 0x44000
|
||||
#define CONFIG_ENV_SIZE 0x4000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user