clk: ti: am33xx: add DPLL clock drivers
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM33xx device. The AM33xx device integrates five different DPLLs: * Core DPLL * Per DPLL * LCD DPLL * DDR DPLL * MPU DPLL The patch adds support for the compatible strings: * "ti,am3-dpll-core-clock" * "ti,am3-dpll-no-gate-clock" * "ti,am3-dpll-no-gate-j-type-clock" * "ti,am3-dpll-x2-clock" The code is loosely based on the drivers/clk/ti/dpll.c drivers of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/dpll.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
This commit is contained in:
Dario Binacchi
Lokesh Vutla
parent
9d76120083
commit
756d64e43e
@ -3,6 +3,13 @@
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# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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#
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config CLK_TI_AM3_DPLL
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bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers"
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depends on CLK && OF_CONTROL
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help
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This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
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provides all interface clocks and functional clocks to the processor.
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config CLK_TI_MUX
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bool "TI mux clock driver"
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depends on CLK && OF_CONTROL && CLK_CCF
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@ -3,4 +3,5 @@
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# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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#
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obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
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obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
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79
drivers/clk/ti/clk-am3-dpll-x2.c
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79
drivers/clk/ti/clk-am3-dpll-x2.c
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@ -0,0 +1,79 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI DPLL x2 clock support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* Loosely based on Linux kernel drivers/clk/ti/dpll.c
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <linux/clk-provider.h>
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struct clk_ti_am3_dpll_x2_priv {
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struct clk parent;
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};
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static ulong clk_ti_am3_dpll_x2_get_rate(struct clk *clk)
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{
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struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(clk->dev);
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unsigned long rate;
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rate = clk_get_rate(&priv->parent);
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if (IS_ERR_VALUE(rate))
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return rate;
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rate *= 2;
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dev_dbg(clk->dev, "rate=%ld\n", rate);
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return rate;
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}
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const struct clk_ops clk_ti_am3_dpll_x2_ops = {
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.get_rate = clk_ti_am3_dpll_x2_get_rate,
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};
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static int clk_ti_am3_dpll_x2_remove(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_release_all(&priv->parent, 1);
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if (err) {
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dev_err(dev, "failed to release parent clock\n");
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return err;
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}
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return 0;
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}
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static int clk_ti_am3_dpll_x2_probe(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_get_by_index(dev, 0, &priv->parent);
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if (err) {
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dev_err(dev, "%s: failed to get parent clock\n", __func__);
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return err;
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}
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return 0;
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}
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static const struct udevice_id clk_ti_am3_dpll_x2_of_match[] = {
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{.compatible = "ti,am3-dpll-x2-clock"},
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{}
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};
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U_BOOT_DRIVER(clk_ti_am3_dpll_x2) = {
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.name = "ti_am3_dpll_x2_clock",
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.id = UCLASS_CLK,
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.of_match = clk_ti_am3_dpll_x2_of_match,
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.probe = clk_ti_am3_dpll_x2_probe,
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.remove = clk_ti_am3_dpll_x2_remove,
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.priv_auto = sizeof(struct clk_ti_am3_dpll_x2_priv),
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.ops = &clk_ti_am3_dpll_x2_ops,
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};
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268
drivers/clk/ti/clk-am3-dpll.c
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268
drivers/clk/ti/clk-am3-dpll.c
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@ -0,0 +1,268 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI DPLL clock support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* Loosely based on Linux kernel drivers/clk/ti/dpll.c
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <hang.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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struct clk_ti_am3_dpll_drv_data {
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ulong max_rate;
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};
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struct clk_ti_am3_dpll_priv {
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fdt_addr_t clkmode_reg;
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fdt_addr_t idlest_reg;
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fdt_addr_t clksel_reg;
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struct clk clk_bypass;
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struct clk clk_ref;
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u16 last_rounded_mult;
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u8 last_rounded_div;
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ulong max_rate;
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};
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static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
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ulong ret, ref_rate, r;
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int m, d, err_min, err;
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int mult = INT_MAX, div = INT_MAX;
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if (priv->max_rate && rate > priv->max_rate) {
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dev_warn(clk->dev, "%ld is to high a rate, lowered to %ld\n",
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rate, priv->max_rate);
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rate = priv->max_rate;
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}
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ret = -EFAULT;
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err = rate;
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err_min = rate;
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ref_rate = clk_get_rate(&priv->clk_ref);
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for (d = 1; err_min && d <= 128; d++) {
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for (m = 2; m <= 2047; m++) {
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r = (ref_rate * m) / d;
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err = abs(r - rate);
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if (err < err_min) {
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err_min = err;
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ret = r;
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mult = m;
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div = d;
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if (err == 0)
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break;
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} else if (r > rate) {
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break;
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}
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}
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}
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priv->last_rounded_mult = mult;
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priv->last_rounded_div = div;
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dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, mult=%d, div=%d\n", rate,
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ret, mult, div);
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return ret;
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}
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static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
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u32 v;
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ulong round_rate;
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round_rate = clk_ti_am3_dpll_round_rate(clk, rate);
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if (IS_ERR_VALUE(round_rate))
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return round_rate;
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v = readl(priv->clksel_reg);
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/* enter bypass mode */
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clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
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/* wait for bypass mode */
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
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(void *)priv->idlest_reg, LDELAY))
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dev_err(clk->dev, "failed bypassing dpll\n");
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/* set M & N */
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v &= ~CM_CLKSEL_DPLL_M_MASK;
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v |= (priv->last_rounded_mult << CM_CLKSEL_DPLL_M_SHIFT) &
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CM_CLKSEL_DPLL_M_MASK;
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v &= ~CM_CLKSEL_DPLL_N_MASK;
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v |= ((priv->last_rounded_div - 1) << CM_CLKSEL_DPLL_N_SHIFT) &
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CM_CLKSEL_DPLL_N_MASK;
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writel(v, priv->clksel_reg);
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/* lock dpll */
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clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
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/* wait till the dpll locks */
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
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(void *)priv->idlest_reg, LDELAY)) {
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dev_err(clk->dev, "failed locking dpll\n");
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hang();
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}
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return round_rate;
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}
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static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
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u64 rate;
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u32 m, n, v;
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/* Return bypass rate if DPLL is bypassed */
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v = readl(priv->clkmode_reg);
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v &= CM_CLKMODE_DPLL_EN_MASK;
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v >>= CM_CLKMODE_DPLL_EN_SHIFT;
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switch (v) {
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case DPLL_EN_MN_BYPASS:
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case DPLL_EN_LOW_POWER_BYPASS:
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case DPLL_EN_FAST_RELOCK_BYPASS:
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rate = clk_get_rate(&priv->clk_bypass);
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dev_dbg(clk->dev, "rate=%lld\n", rate);
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return rate;
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}
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v = readl(priv->clksel_reg);
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m = v & CM_CLKSEL_DPLL_M_MASK;
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m >>= CM_CLKSEL_DPLL_M_SHIFT;
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n = v & CM_CLKSEL_DPLL_N_MASK;
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n >>= CM_CLKSEL_DPLL_N_SHIFT;
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rate = clk_get_rate(&priv->clk_ref) * m;
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do_div(rate, n + 1);
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dev_dbg(clk->dev, "rate=%lld\n", rate);
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return rate;
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}
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const struct clk_ops clk_ti_am3_dpll_ops = {
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.round_rate = clk_ti_am3_dpll_round_rate,
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.get_rate = clk_ti_am3_dpll_get_rate,
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.set_rate = clk_ti_am3_dpll_set_rate,
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};
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static int clk_ti_am3_dpll_remove(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_release_all(&priv->clk_bypass, 1);
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if (err) {
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dev_err(dev, "failed to release bypass clock\n");
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return err;
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}
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err = clk_release_all(&priv->clk_ref, 1);
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if (err) {
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dev_err(dev, "failed to release reference clock\n");
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return err;
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}
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return 0;
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}
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static int clk_ti_am3_dpll_probe(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_get_by_index(dev, 0, &priv->clk_ref);
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if (err) {
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dev_err(dev, "failed to get reference clock\n");
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return err;
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}
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err = clk_get_by_index(dev, 1, &priv->clk_bypass);
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if (err) {
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dev_err(dev, "failed to get bypass clock\n");
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return err;
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}
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return 0;
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}
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static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
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struct clk_ti_am3_dpll_drv_data *data =
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(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
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priv->max_rate = data->max_rate;
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priv->clkmode_reg = dev_read_addr_index(dev, 0);
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if (priv->clkmode_reg == FDT_ADDR_T_NONE) {
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dev_err(dev, "failed to get clkmode register\n");
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return -EINVAL;
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}
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dev_dbg(dev, "clkmode_reg=0x%08lx\n", priv->clkmode_reg);
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priv->idlest_reg = dev_read_addr_index(dev, 1);
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if (priv->idlest_reg == FDT_ADDR_T_NONE) {
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dev_err(dev, "failed to get idlest register\n");
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return -EINVAL;
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}
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dev_dbg(dev, "idlest_reg=0x%08lx\n", priv->idlest_reg);
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priv->clksel_reg = dev_read_addr_index(dev, 2);
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if (priv->clksel_reg == FDT_ADDR_T_NONE) {
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dev_err(dev, "failed to get clksel register\n");
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return -EINVAL;
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}
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dev_dbg(dev, "clksel_reg=0x%08lx\n", priv->clksel_reg);
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return 0;
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}
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static const struct clk_ti_am3_dpll_drv_data dpll_no_gate_data = {
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.max_rate = 1000000000
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};
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static const struct clk_ti_am3_dpll_drv_data dpll_no_gate_j_type_data = {
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.max_rate = 2000000000
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};
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static const struct clk_ti_am3_dpll_drv_data dpll_core_data = {
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.max_rate = 1000000000
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};
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static const struct udevice_id clk_ti_am3_dpll_of_match[] = {
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{.compatible = "ti,am3-dpll-core-clock",
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.data = (ulong)&dpll_core_data},
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{.compatible = "ti,am3-dpll-no-gate-clock",
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.data = (ulong)&dpll_no_gate_data},
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{.compatible = "ti,am3-dpll-no-gate-j-type-clock",
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.data = (ulong)&dpll_no_gate_j_type_data},
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{}
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};
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U_BOOT_DRIVER(clk_ti_am3_dpll) = {
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.name = "ti_am3_dpll_clock",
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.id = UCLASS_CLK,
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.of_match = clk_ti_am3_dpll_of_match,
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.ofdata_to_platdata = clk_ti_am3_dpll_of_to_plat,
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.probe = clk_ti_am3_dpll_probe,
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.remove = clk_ti_am3_dpll_remove,
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.priv_auto = sizeof(struct clk_ti_am3_dpll_priv),
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.ops = &clk_ti_am3_dpll_ops,
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};
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