configs: Migrate CONFIG_SPL_FRAMEWORK

Migrate the option CONFIG_SPL_FRAMEWORK and make this gate most of the
current set of options we have in Kconfig.  We will need to have some
options available for SPL and !SPL_FRAMEWORK so this is important.  In a
few cases we re-order existing options so that we have less escapes from
the SPL_FRAMEWORK guard.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2018-02-06 12:15:38 -05:00
parent 7a88afd080
commit 75670c81e4
208 changed files with 137 additions and 102 deletions

View File

@@ -228,7 +228,6 @@
GENERATED_GBL_DATA_SIZE)
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)

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@@ -214,7 +214,6 @@
#define CONFIG_ENV_ADDR 0x260000
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000

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@@ -106,7 +106,6 @@
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x010000
#define CONFIG_SPL_STACK 0x310000

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@@ -155,7 +155,6 @@
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x6000
#define CONFIG_SPL_STACK 0x308000

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@@ -129,7 +129,6 @@
#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x6000
#define CONFIG_SPL_STACK 0x308000

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@@ -79,7 +79,6 @@
* under common/spl/. Given our generally common memory map, we set a
* number of related defaults and sizes here.
*/
#define CONFIG_SPL_FRAMEWORK
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the

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@@ -19,8 +19,6 @@
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x003f8000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0xfffd0000
#define BOOT_DEVICE_SPI 10

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@@ -86,7 +86,6 @@
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SIZE (140 << 10)
#define CONFIG_SPL_TEXT_BASE 0x40000030
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)

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@@ -219,7 +219,6 @@
#define CONFIG_SCF0403_LCD
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"

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@@ -94,7 +94,6 @@
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SIZE (160 << 10)
#if defined(CONFIG_SECURED_MODE_IMAGE)

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@@ -115,7 +115,6 @@
SZ_4M, 0x1000)
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
#define CONFIG_SPL_STACK (SZ_16K)

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@@ -294,7 +294,6 @@
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN

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@@ -69,7 +69,6 @@
/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)

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@@ -72,7 +72,6 @@
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SIZE (140 << 10)
#define CONFIG_SPL_TEXT_BASE 0x40000030
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)

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@@ -86,7 +86,6 @@
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SIZE (140 << 10)
#define CONFIG_SPL_TEXT_BASE 0x40000030
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)

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@@ -81,7 +81,6 @@
/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)

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@@ -172,7 +172,6 @@
#define CONFIG_SPL_STACK 0x0000FFF8
/* Use the framework and generic lib */
#define CONFIG_SPL_FRAMEWORK
/* SPL will use serial */

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@@ -90,7 +90,6 @@
/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)

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@@ -16,7 +16,6 @@
* SPL
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0xffff0000
#define CONFIG_SPL_MAX_SIZE 0x0000fff0
#define CONFIG_SPL_STACK 0x00020000

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@@ -8,9 +8,6 @@
#define __IMX6_SPL_CONFIG_H
#ifdef CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
/*
* see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals:
* - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF

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@@ -12,9 +12,6 @@
#define __IMX7_SPL_CONFIG_H
#ifdef CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
/*
* see figure 6-22 in i.MX 7Dual/Solo Reference manuals:
* - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to

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@@ -226,7 +226,6 @@
#define CONFIG_MTD_PARTITIONS
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN

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@@ -75,8 +75,6 @@
* SPL
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)

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@@ -61,7 +61,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT

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@@ -51,7 +51,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
@@ -68,7 +67,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000

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@@ -66,7 +66,6 @@
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK
#ifdef CONFIG_SECURE_BOOT
/*

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@@ -65,7 +65,6 @@
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
@@ -96,7 +95,6 @@
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000

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@@ -63,7 +63,6 @@
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -102,7 +101,6 @@
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT

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@@ -242,7 +242,6 @@ unsigned long long get_qixis_addr(void);
#ifdef CONFIG_SPL
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)

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@@ -217,7 +217,6 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"

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@@ -173,7 +173,6 @@
/*
* NAND SPL
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
#define CONFIG_SPL_TEXT_BASE 0x70008000
#define CONFIG_SPL_PAD_TO 0x8000

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@@ -197,7 +197,6 @@
"fi ; " \
"fi\0"
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

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@@ -65,7 +65,6 @@
/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)

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@@ -256,7 +256,6 @@
GENERATED_GBL_DATA_SIZE)
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS

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@@ -217,7 +217,6 @@
#endif
/* SPL part */
#define CONFIG_SPL_FRAMEWORK
#ifdef CONFIG_SYS_FLASH_BASE
# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE

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@@ -23,8 +23,6 @@
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS

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@@ -28,8 +28,6 @@
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS

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@@ -38,7 +38,6 @@
* order to allow for BCH8 to fit in.
*/
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */

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@@ -19,7 +19,6 @@
#include <configs/ti_omap3_common.h>
/* Remove SPL boot option - we do not support that on LDP yet */
#undef CONFIG_SPL_FRAMEWORK
/* Generic NAND definition conflicts with debug_base */
#undef CONFIG_SYS_NAND_BASE

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@@ -282,7 +282,6 @@
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN

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@@ -119,7 +119,6 @@
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x010000
#define CONFIG_SPL_STACK 0x310000

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@@ -36,8 +36,6 @@
/* SPI is not supported */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0xfffd0000
#define BOOT_DEVICE_SPI 10

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@@ -36,7 +36,6 @@
#define CONFIG_SPL_TEXT_BASE 0x10080800
/* spl size 32kb sram - 2kb bootrom */
#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
#define CONFIG_SPL_FRAMEWORK 1
#define CONFIG_ROCKCHIP_SERIAL 1
#define CONFIG_SPL_STACK 0x10087fff

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@@ -18,7 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800

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@@ -19,7 +19,6 @@
#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM

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@@ -24,7 +24,6 @@
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000

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@@ -13,7 +13,6 @@
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SPL_FRAMEWORK
#if defined(CONFIG_SPL_SPI_SUPPORT)
#define CONFIG_SPL_SPI_LOAD
#endif

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@@ -67,7 +67,6 @@
#endif
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

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@@ -47,7 +47,6 @@
#endif
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

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@@ -70,7 +70,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

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@@ -90,7 +90,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

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@@ -48,7 +48,6 @@
#endif
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

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@@ -46,7 +46,6 @@
#endif
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

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@@ -8,6 +8,4 @@
#include <configs/sandbox.h>
#define CONFIG_SPL_FRAMEWORK
#endif

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@@ -99,7 +99,6 @@
#define CONFIG_SYS_I2C
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)

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@@ -195,7 +195,6 @@
#endif
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SPL_MAX_SIZE (SZ_4K)

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@@ -70,8 +70,6 @@
* SPL
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)

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@@ -257,7 +257,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* 0xFFFF_zzzz ...... Global Data
* 0xFFFF_FF00 ...... End of SRAM
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE

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@@ -70,7 +70,6 @@
/* For SPL */
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_SPL_LEN 0x00008000

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@@ -184,8 +184,6 @@
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
#define CONFIG_SPL_FRAMEWORK
#ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif

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@@ -148,7 +148,6 @@
#define CONFIG_NET_RETRY_COUNT 10
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */

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@@ -204,7 +204,6 @@
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"

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@@ -152,7 +152,6 @@
ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000)
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SPL_MAX_SIZE (31 * SZ_512)
#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K)

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@@ -88,7 +88,6 @@
#ifndef CONFIG_ARM64
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000

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@@ -108,7 +108,6 @@
/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)

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@@ -127,7 +127,6 @@
#define CONFIG_CONS_INDEX 1
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)

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@@ -148,7 +148,6 @@
*/
#if !defined(CONFIG_NOR_BOOT) && \
!(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
#define CONFIG_SPL_FRAMEWORK
/*
* We also support Falcon Mode so that the Linux kernel can be booted

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@@ -228,7 +228,6 @@
#define CONFIG_SYS_SRAM_SIZE 0x10000
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS

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@@ -83,7 +83,6 @@
"initrd_high=0x10000000\0"
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SIZE (140 << 10)
#define CONFIG_SPL_TEXT_BASE 0x40000030
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)

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@@ -228,8 +228,6 @@
#define CONFIG_SPL_STACK (0x00100000)
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
/* subtract sizeof(struct image_header) */

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@@ -128,7 +128,6 @@
#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x6000
#define CONFIG_SPL_STACK 0x308000

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@@ -113,7 +113,6 @@
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

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@@ -19,7 +19,6 @@
/*
* SPL
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x10002300
#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */

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@@ -153,7 +153,6 @@
/* SPL will use SRAM as stack */
#define CONFIG_SPL_STACK 0x0000FFF8
/* Use the framework and generic lib */
#define CONFIG_SPL_FRAMEWORK
/* SPL will use serial */
/* SPL will load U-Boot from NAND offset 0x40000 */
#define CONFIG_SPL_NAND_DRIVERS

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@@ -221,8 +221,6 @@
#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
#define CONFIG_SPL_FRAMEWORK
/*
* Please select/define only one of the following
* Each definition corresponds to a supported DDR chip.

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@@ -229,8 +229,6 @@
#define CONFIG_SPL_BSS_START_ADDR 0x0
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SPL_FRAMEWORK
#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
# define CONFIG_SPL_SPI_LOAD
# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000

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@@ -293,7 +293,6 @@
/* Commands */
/* SPL part */
#define CONFIG_SPL_FRAMEWORK
/* MMC support */
#ifdef CONFIG_MMC_SDHCI_ZYNQ