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Merge branch '2019-07-26-ti-imports'

Browse Source 
- Bring in the rest of the J271E platform
- Various OMAP3/AM3517, DA850 fixes
This commit is contained in:
Tom Rini 2019-07-27 19:50:52 -04:00
commit 75551c8bfc
87 changed files with 2577 additions and 378 deletions
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2
arch/arm/dts/Makefile
View File

@ -773,6 +773,8 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
stm32mp157c-ev1.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \

36
arch/arm/dts/am3517-evm-u-boot.dtsi
View File

@ -4,20 +4,40 @@
* Logic PD - http://www.logicpd.com
*/
#include "omap3-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart3;
aliases {
/delete-property/ serial0;
/delete-property/ serial1;
};
ocp@68000000 {
/delete-node/ bandgap@48002524;
};
};
&uart1 {
reg-shift = <2>;
&gpio1 {
/delete-property/ u-boot,dm-spl;
};
&uart2 {
reg-shift = <2>;
&gpio2 {
/delete-property/ u-boot,dm-spl;
};
&uart3 {
reg-shift = <2>;
&gpio3 {
/delete-property/ u-boot,dm-spl;
};
&gpio5 {
/delete-property/ u-boot,dm-spl;
};
&gpio6 {
/delete-property/ u-boot,dm-spl;
};
/delete-node/ &uart1;
/delete-node/ &uart2;
/delete-node/ &mmc2;
/delete-node/ &mmc3;

10
arch/arm/dts/am571x-idk.dts
View File

@ -11,6 +11,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
/ {
@ -101,14 +102,9 @@
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {

10
arch/arm/dts/am572x-idk.dts
View File

@ -11,6 +11,7 @@
#include "dra74x.dtsi"
#include "am572x-idk-common.dtsi"
#include "am57xx-idk-common.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
/ {
@ -20,14 +21,9 @@
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {

15
arch/arm/dts/am574x-idk.dts
View File

@ -7,6 +7,8 @@
/dts-v1/;
#include "dra76x.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra76x-mmc-iodelay.dtsi"
#include "am572x-idk-common.dtsi"
/ {
@ -20,3 +22,16 @@
spi-max-frequency = <96000000>;
};
};
&mmc1 {
pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_default>;
pinctrl-2 = <&mmc2_pins_default>;
};

1
arch/arm/dts/am57xx-beagle-x15-common.dtsi
View File

@ -433,6 +433,7 @@
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
no-1-8-v;
};
&mmc2 {

7
arch/arm/dts/am57xx-beagle-x15-revb1.dts
View File

@ -19,14 +19,9 @@
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&ldo1_reg>;
};

7
arch/arm/dts/am57xx-beagle-x15-revc.dts
View File

@ -19,14 +19,9 @@
};
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&ldo1_reg>;
};

1
arch/arm/dts/am57xx-idk-common.dtsi
View File

@ -405,6 +405,7 @@
vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
no-1-8-v;
};
&mmc2 {

19
arch/arm/dts/dra7-mmc-iodelay.dtsi Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MMC IOdelay values for TI's DRA7xx SoCs.
* Copyright (C) 2019 Texas Instruments
* Author: Faiz Abbas <faiz_abbas@ti.com>
*/
&dra7_pmx_core {
mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
};

40
arch/arm/dts/dra76x-mmc-iodelay.dtsi
View File

@ -22,7 +22,7 @@
*
* Datamanual Revisions:
*
* DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
* DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018
*
*/
@ -169,25 +169,25 @@
/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
pinctrl-pin-array = <
0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
>;
};

10
arch/arm/dts/k3-am65-main.dtsi
View File

@ -89,7 +89,7 @@
sdhci0: sdhci@4f80000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
power-domains = <&k3_pds 47>;
power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
clock-names = "clk_ahb", "clk_xin";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
@ -108,7 +108,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
@ -119,7 +119,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@2020000 {
@ -130,7 +130,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@2030000 {
@ -141,6 +141,6 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
};
};

2
arch/arm/dts/k3-am65-mcu.dtsi
View File

@ -24,6 +24,6 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
};
};

4
arch/arm/dts/k3-am65-wakeup.dtsi
View File

@ -20,7 +20,7 @@
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <1>;
#power-domain-cells = <2>;
};
k3_clks: clocks {
@ -60,6 +60,6 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
};
};

1
arch/arm/dts/k3-am65.dtsi
View File

@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 AM654 SoC";

2
arch/arm/dts/k3-am654-base-board-u-boot.dtsi
View File

@ -26,7 +26,7 @@
reg = <0x0 0x4FA0000 0x0 0x1000>,
<0x0 0x4FB0000 0x0 0x400>;
clocks = <&k3_clks 48 1>;
power-domains = <&k3_pds 48>;
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
max-frequency = <25000000>;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;

4
arch/arm/dts/k3-am654-ddr.dtsi
View File

@ -11,8 +11,8 @@
<0x0 0x02988000 0x0 0x2000>;
reg-names = "ss", "ctl", "phy";
clocks = <&k3_clks 20 0>;
power-domains = <&k3_pds 20>,
<&k3_pds 244>;
power-domains = <&k3_pds 20 TI_SCI_PD_SHARED>,
<&k3_pds 244 TI_SCI_PD_SHARED>;
assigned-clocks = <&k3_clks 20 1>;
assigned-clock-rates = <DDR_PLL_FREQUENCY>;
u-boot,dm-spl;

8
arch/arm/dts/k3-am654-r5-base-board.dts
View File

@ -32,8 +32,8 @@
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61>,
<&k3_pds 202>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
assigned-clocks = <&k3_clks 202 0>;
assigned-clock-rates = <800000000>;
@ -118,6 +118,10 @@
status = "okay";
};
&main_uart0 {
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_pmx0 {
u-boot,dm-spl;
wkup_uart0_pins_default: wkup_uart0_pins_default {

75
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi Normal file
View File

@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
};
&cbass_main{
u-boot,dm-spl;
};
&cbass_mcu_wakeup {
u-boot,dm-spl;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
u-boot,dm-spl;
};
};
&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
u-boot,dm-spl;
};
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&wkup_pmx0 {
u-boot,dm-spl;
};
&main_pmx0 {
u-boot,dm-spl;
};
&main_uart0 {
u-boot,dm-spl;
};
&mcu_uart0 {
u-boot,dm-spl;
};
&main_sdhci0 {
u-boot,dm-spl;
};
&main_sdhci1 {
u-boot,dm-spl;
};

63
arch/arm/dts/k3-j721e-common-proc-board.dts Normal file
View File

@ -0,0 +1,63 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "k3-j721e-som-p0.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
};
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "disabled";
};
&main_uart3 {
/* UART not brought out */
status = "disabled";
};
&main_uart5 {
/* UART not brought out */
status = "disabled";
};
&main_uart6 {
/* UART not brought out */
status = "disabled";
};
&main_uart7 {
/* UART not brought out */
status = "disabled";
};
&main_uart8 {
/* UART not brought out */
status = "disabled";
};
&main_uart9 {
/* UART not brought out */
status = "disabled";
};
&main_sdhci0 {
/* eMMC */
voltage-ranges = <1800 1800>;
non-removable;
ti,driver-strength-ohm = <50>;
};
&main_sdhci1 {
/* SD/MMC */
voltage-ranges = <1800 1800 3300 3300>;
ti,driver-strength-ohm = <50>;
};

231
arch/arm/dts/k3-j721e-main.dtsi Normal file
View File

@ -0,0 +1,231 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721E SoC Family Main Domain peripherals
*
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x0 0x70000000 0x0 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x70000000 0x800000>;
atf-sram@0 {
reg = <0x0 0x20000>;
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01900000 0x00 0x100000>; /* GICR */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: gic-its@18200000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
smmu0: smmu@36600000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x36600000 0x0 0x100000>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "gerror";
#iommu-cells = <1>;
};
secure_proxy_main: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x32c00000 0x00 0x100000>,
<0x00 0x32400000 0x00 0x100000>,
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
main_pmx0: pinmux@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x0 0x11c000 0x0 0x2b4>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
};
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 0>;
clock-names = "fclk";
};
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 0>;
clock-names = "fclk";
};
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 0>;
clock-names = "fclk";
};
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 0>;
clock-names = "fclk";
};
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 0>;
clock-names = "fclk";
};
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 0>;
clock-names = "fclk";
};
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 0>;
clock-names = "fclk";
};
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 0>;
clock-names = "fclk";
};
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 0>;
clock-names = "fclk";
};
main_sdhci0: sdhci@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
assigned-clocks = <&k3_clks 91 1>;
assigned-clock-parents = <&k3_clks 91 2>;
bus-width = <8>;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
main_sdhci1: sdhci@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
*
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
&cbass_mcu_wakeup {
dmsc: dmsc@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x0 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clocks {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
ti,scan-clocks-from-dt;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
wkup_pmx0: pinmux@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 0>;
clock-names = "fclk";
};
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "k3-j721e-som-p0.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
u-boot,dm-spl;
};
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
u-boot,dm-spl;
};
};
&cbass_mcu_wakeup {
mcu_secproxy: secproxy@28380000 {
u-boot,dm-spl;
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>,
<0x0 0x2a480000 0x0 0x80000>;
reg-names = "rt", "scfg", "target_data";
#mbox-cells = <1>;
};
sysctrler: sysctrler {
u-boot,dm-spl;
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
};
};
&dmsc {
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
&wkup_pmx0 {
wkup_uart0_pins_default: wkup_uart0_pins_default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>;
};
mcu_uart0_pins_default: mcu_uart0_pins_default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
};
&main_pmx0 {
main_uart0_pins_default: main_uart0_pins_default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
};
};
&wkup_uart0 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
};
&mcu_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
status = "okay";
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&main_sdhci0 {
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
ti,driver-strength-ohm = <50>;
non-removable;
bus-width = <8>;
};
&main_sdhci1 {
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
ti,driver-strength-ohm = <50>;
};
#include "k3-j721e-common-proc-board-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "k3-j721e.dtsi"
/ {
memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
alignment = <0x1000>;
no-map;
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721E SoC Family
*
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 J721E SoC";
compatible = "ti,j721e";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
serial5 = &main_uart3;
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
serial9 = &main_uart7;
serial10 = &main_uart8;
serial11 = &main_uart9;
};
chosen { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a72";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a72";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <2048>;
next-level-cache = <&msmc_l3>;
};
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a72_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: interconnect@100000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
/* MCUSS_WKUP Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: interconnect@28380000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
};
};
};
/* Now include the peripherals for each bus segments */
#include "k3-j721e-main.dtsi"
#include "k3-j721e-mcu-wakeup.dtsi"

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@ -1,8 +1,4 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

6
arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
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@ -1,8 +1,4 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

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arch/arm/dts/logicpd-som-lv-baseboard.dtsi
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@ -1,8 +1,4 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0-only
/ {
gpio_keys {
@ -153,7 +149,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */
cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
vmmc-supply = <&vmmc1>;
bus-width = <4>;
cap-power-off-card;

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@ -1,8 +1,4 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/input/input.h>

6
arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
View File

@ -1,8 +1,4 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

6
arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
View File

@ -1,8 +1,4 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

6
arch/arm/dts/logicpd-torpedo-baseboard.dtsi
View File

@ -1,8 +1,4 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0-only
/ {
gpio_keys {

6
arch/arm/dts/logicpd-torpedo-som.dtsi
View File

@ -1,8 +1,4 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/input/input.h>

13
arch/arm/mach-k3/Kconfig
View File

@ -7,6 +7,9 @@ choice
config SOC_K3_AM6
bool "TI's K3 based AM6 SoC Family Support"
config SOC_K3_J721E
bool "TI's K3 based J721E SoC Family Support"
endchoice
config SYS_SOC
@ -14,7 +17,8 @@ config SYS_SOC
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
default 0x80000
default 0x80000 if SOC_K3_AM6
default 0x100000 if SOC_K3_J721E
help
Describes the total size of the MCU MSRAM. This doesn't
specify the total size of SPL as ROM can use some part
@ -23,7 +27,8 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000
default 0x58000 if SOC_K3_AM6
default 0xc0000 if SOC_K3_J721E
help
Describes the maximum size of the image that ROM can download
from any boot media.
@ -31,18 +36,21 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x40280000 if SOC_K3_AM6
default 0x40280000 if SOC_K3_J721E
help
Describes the base address of MCU Scratchpad RAM.
config SYS_K3_MCU_SCRATCHPAD_SIZE
hex
default 0x200 if SOC_K3_AM6
default 0x200 if SOC_K3_J721E
help
Describes the size of MCU Scratchpad RAM.
config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM6
default 0x41cffc00 if SOC_K3_J721E
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
@ -105,4 +113,5 @@ config SYS_K3_SPL_ATF
after SPL from R5.
source "board/ti/am65x/Kconfig"
source "board/ti/j721e/Kconfig"
endif

1
arch/arm/mach-k3/Makefile
View File

@ -4,6 +4,7 @@
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o

60
arch/arm/mach-k3/am6_init.c
View File

@ -16,6 +16,7 @@
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#ifdef CONFIG_SPL_BUILD
static void mmr_unlock(u32 base, u32 partition)
@ -209,8 +210,63 @@ u32 spl_boot_device(void)
}
#endif
#ifndef CONFIG_SYSRESET
void reset_cpu(ulong ignored)
#ifdef CONFIG_SYS_K3_SPL_ATF
#define AM6_DEV_MCU_RTI0 134
#define AM6_DEV_MCU_RTI1 135
#define AM6_DEV_MCU_ARMSS0_CPU0 159
#define AM6_DEV_MCU_ARMSS0_CPU1 245
void release_resources_for_core_shutdown(void)
{
struct udevice *dev;
struct ti_sci_handle *ti_sci;
struct ti_sci_dev_ops *dev_ops;
struct ti_sci_proc_ops *proc_ops;
int ret;
u32 i;
const u32 put_device_ids[] = {
AM6_DEV_MCU_RTI0,
AM6_DEV_MCU_RTI1,
};
/* Get handle to Device Management and Security Controller (SYSFW) */
ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &dev);
if (ret)
panic("Failed to get handle to SYSFW (%d)\n", ret);
ti_sci = (struct ti_sci_handle *)(ti_sci_get_handle_from_sysfw(dev));
dev_ops = &ti_sci->ops.dev_ops;
proc_ops = &ti_sci->ops.proc_ops;
/* Iterate through list of devices to put (shutdown) */
for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
u32 id = put_device_ids[i];
ret = dev_ops->put_device(ti_sci, id);
if (ret)
panic("Failed to put device %u (%d)\n", id, ret);
}
const u32 put_core_ids[] = {
AM6_DEV_MCU_ARMSS0_CPU1,
AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
};
/* Iterate through list of cores to put (shutdown) */
for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
u32 id = put_core_ids[i];
/*
* Queue up the core shutdown request. Note that this call
* needs to be followed up by an actual invocation of an WFE
* or WFI CPU instruction.
*/
ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
if (ret)
panic("Failed sending core %u shutdown message (%d)\n",
id, ret);
}
}
#endif

55
arch/arm/mach-k3/arm64-mmu.c
View File

@ -12,6 +12,7 @@
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#ifdef CONFIG_SOC_K3_AM6
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
@ -43,3 +44,57 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
};
struct mm_region *mem_map = am654_mem_map;
#endif /* CONFIG_SOC_K3_AM6 */
#ifdef CONFIG_SOC_K3_J721E
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x0bc00000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0xabc00000UL,
.phys = 0xabc00000UL,
.size = 0x54400000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j721e_mem_map;
#endif /* CONFIG_SOC_K3_J721E */

16
arch/arm/mach-k3/common.c
View File

@ -13,6 +13,7 @@
#include <remoteproc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <fdt_support.h>
#include <asm/arch/sys_proto.h>
struct ti_sci_handle *get_ti_sci_handle(void)
{
@ -29,8 +30,12 @@ struct ti_sci_handle *get_ti_sci_handle(void)
#ifdef CONFIG_SYS_K3_SPL_ATF
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
int ret;
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
/*
* It is assumed that remoteproc device 1 is the corresponding
* Cortex-A core which runs ATF. Make sure DT reflects the same.
@ -51,7 +56,10 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
debug("ATF started. Waiting indefinitely...\n");
debug("Releasing resources...\n");
release_resources_for_core_shutdown();
debug("Finalizing core shutdown...\n");
while (1)
asm volatile("wfe");
}
@ -130,3 +138,9 @@ int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
return 0;
}
#endif
#ifndef CONFIG_SYSRESET
void reset_cpu(ulong ignored)
{
}
#endif

4
arch/arm/mach-k3/include/mach/hardware.h
View File

@ -9,4 +9,8 @@
#ifdef CONFIG_SOC_K3_AM6
#include "am6_hardware.h"
#endif
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_hardware.h"
#endif
#endif /* _ASM_ARCH_HARDWARE_H_ */

49
arch/arm/mach-k3/include/mach/j721e_hardware.h Normal file
View File

@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* K3: J721E SoC definitions, structures etc.
*
* (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#ifndef __ASM_ARCH_J721E_HARDWARE_H
#define __ASM_ARCH_J721E_HARDWARE_H
#include <config.h>
#define CTRL_MMR0_BASE 0x00100000
#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
#define WKUP_CTRL_MMR0_BASE 0x43000000
#define MCU_CTRL_MMR0_BASE 0x40f00000
#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
/*
* The CTRL_MMR0 memory space is divided into several equally-spaced
* partitions, so defining the partition size allows us to determine
* register addresses common to those partitions.
*/
#define CTRL_MMR0_PARTITION_SIZE 0x4000
/*
* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
* shared register definitions.
*/
#define CTRLMMR_LOCK_KICK0 0x01008
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
#define CTRLMMR_LOCK_KICK1 0x0100c
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
#endif /* __ASM_ARCH_J721E_HARDWARE_H */

31
arch/arm/mach-k3/include/mach/j721e_spl.h Normal file
View File

@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_J721E_SPL_H_
#define _ASM_ARCH_J721E_SPL_H_
/* With BootMode B = 0 */
#define BOOT_DEVICE_HYPERFLASH 0x00
#define BOOT_DEVICE_OSPI 0x01
#define BOOT_DEVICE_QSPI 0x02
#define BOOT_DEVICE_SPI 0x03
#define BOOT_DEVICE_ETHERNET 0x04
#define BOOT_DEVICE_I2C 0x06
#define BOOT_DEVICE_UART 0x07
/* With BootMode B = 1 */
#define BOOT_DEVICE_MMC2 0x10
#define BOOT_DEVICE_MMC1 0x11
#define BOOT_DEVICE_USB 0x12
#define BOOT_DEVICE_UFS 0x13
#define BOOT_DEVIE_GPMC 0x14
#define BOOT_DEVICE_PCIE 0x15
#define BOOT_DEVICE_MMC2_2 0x16
#define BOOT_DEVICE_RAM 0x17
#define BOOT_MODE_B_SHIFT 4
#define BOOT_MODE_B_MASK BIT(4)
#endif

4
arch/arm/mach-k3/include/mach/spl.h
View File

@ -9,4 +9,8 @@
#ifdef CONFIG_SOC_K3_AM6
#include "am6_spl.h"
#endif
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_spl.h"
#endif
#endif /* _ASM_ARCH_SPL_H_ */

2
arch/arm/mach-k3/include/mach/sys_proto.h
View File

@ -13,5 +13,5 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
struct ti_sci_handle *get_ti_sci_handle(void);
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
int do_board_detect(void);
void release_resources_for_core_shutdown(void);
#endif

228
arch/arm/mach-k3/j721e_init.c Normal file
View File

@ -0,0 +1,228 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* J721E: SoC specific initialization
*
* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/armv7_mpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sysfw-loader.h>
#include "common.h"
#include <asm/arch/sys_proto.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
#ifdef CONFIG_SPL_BUILD
static void mmr_unlock(u32 base, u32 partition)
{
/* Translate the base address */
phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
/* Unlock the requested partition if locked using two-step sequence */
writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
}
static void ctrl_mmr_unlock(void)
{
/* Unlock all WKUP_CTRL_MMR0 module registers */
mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
/* Unlock all MCU_CTRL_MMR0 module registers */
mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
/* Unlock all CTRL_MMR0 module registers */
mmr_unlock(CTRL_MMR0_BASE, 0);
mmr_unlock(CTRL_MMR0_BASE, 1);
mmr_unlock(CTRL_MMR0_BASE, 2);
mmr_unlock(CTRL_MMR0_BASE, 3);
mmr_unlock(CTRL_MMR0_BASE, 4);
mmr_unlock(CTRL_MMR0_BASE, 5);
mmr_unlock(CTRL_MMR0_BASE, 6);
mmr_unlock(CTRL_MMR0_BASE, 7);
}
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
* it to the .data section.
*/
u32 bootindex __attribute__((section(".data")));
static void store_boot_index_from_rom(void)
{
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
}
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW)
struct udevice *dev;
int ret;
#endif
/*
* Cannot delay this further as there is a chance that
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
*/
store_boot_index_from_rom();
/* Make all control module registers accessible */
ctrl_mmr_unlock();
#ifdef CONFIG_CPU_V7R
setup_k3_mpu_regions();
#endif
/* Init DM early */
spl_early_init();
#ifdef CONFIG_K3_LOAD_SYSFW
/*
* Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
* regardless of the result of pinctrl. Do this without probing the
* device, but instead by searching the device that would request the
* given sequence number if probed. The UART will be used by the system
* firmware (SYSFW) image for various purposes and SYSFW depends on us
* to initialize its pin settings.
*/
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
if (!ret)
pinctrl_select_state(dev, "default");
/*
* Load, start up, and configure system controller firmware. Provide
* the U-Boot console init function to the SYSFW post-PM configuration
* callback hook, effectively switching on (or over) the console
* output.
*/
k3_sysfw_loader(preloader_console_init);
#else
/* Prepare console output */
preloader_console_init();
#endif
}
u32 spl_boot_mode(const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
default:
return MMCSD_MODE_RAW;
}
}
static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
{
u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
BOOT_MODE_B_SHIFT;
if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
bootmode = BOOT_DEVICE_SPI;
if (bootmode == BOOT_DEVICE_MMC2) {
u32 port = (main_devstat &
MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
if (port == 0x0)
bootmode = BOOT_DEVICE_MMC1;
}
return bootmode;
}
u32 spl_boot_device(void)
{
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
u32 main_devstat;
if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
printf("ERROR: MCU only boot is not yet supported\n");
return BOOT_DEVICE_RAM;
}
/* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
/* ToDo: Add support for backup boot media */
return __get_primary_bootmedia(main_devstat, wkup_devstat);
}
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF
#define J721E_DEV_MCU_RTI0 262
#define J721E_DEV_MCU_RTI1 263
#define J721E_DEV_MCU_ARMSS0_CPU0 250
#define J721E_DEV_MCU_ARMSS0_CPU1 251
void release_resources_for_core_shutdown(void)
{
struct ti_sci_handle *ti_sci;
struct ti_sci_dev_ops *dev_ops;
struct ti_sci_proc_ops *proc_ops;
int ret;
u32 i;
const u32 put_device_ids[] = {
J721E_DEV_MCU_RTI0,
J721E_DEV_MCU_RTI1,
};
ti_sci = get_ti_sci_handle();
dev_ops = &ti_sci->ops.dev_ops;
proc_ops = &ti_sci->ops.proc_ops;
/* Iterate through list of devices to put (shutdown) */
for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
u32 id = put_device_ids[i];
ret = dev_ops->put_device(ti_sci, id);
if (ret)
panic("Failed to put device %u (%d)\n", id, ret);
}
const u32 put_core_ids[] = {
J721E_DEV_MCU_ARMSS0_CPU1,
J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
};
/* Iterate through list of cores to put (shutdown) */
for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
u32 id = put_core_ids[i];
/*
* Queue up the core shutdown request. Note that this call
* needs to be followed up by an actual invocation of an WFE
* or WFI CPU instruction.
*/
ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
if (ret)
panic("Failed sending core %u shutdown message (%d)\n",
id, ret);
}
}
#endif

9
board/davinci/da8xxevm/da850evm.c
View File

@ -353,10 +353,6 @@ int board_init(void)
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */
clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
@ -377,11 +373,6 @@ int board_init(void)
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return 0;
}

45
board/logicpd/am3517evm/am3517evm.c
View File

@ -113,47 +113,16 @@ static void am3517_evm_musb_init(void)
*/
int misc_init_r(void)
{
volatile unsigned int ctr;
u32 reset;
#if !defined(CONFIG_DM_I2C)
#ifdef CONFIG_SYS_I2C_OMAP24XX
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
#endif
omap_die_id_display();
am3517_evm_musb_init();
if (gpio_request(PHY_GPIO, "gpio_30") == 0) {
/* activate PHY reset */
gpio_direction_output(PHY_GPIO, 0);
gpio_set_value(PHY_GPIO, 0);
ctr = 0;
do {
udelay(1000);
ctr++;
} while (ctr < 300);
/* deactivate PHY reset */
gpio_set_value(PHY_GPIO, 1);
/* allow the PHY to stabilize and settle down */
ctr = 0;
do {
udelay(1000);
ctr++;
} while (ctr < 300);
/* ensure that the module is out of reset */
reset = readl(AM3517_IP_SW_RESET);
reset &= (~CPGMACSS_SW_RST);
writel(reset, AM3517_IP_SW_RESET);
/* Free requested GPIO */
gpio_free(PHY_GPIO);
}
/* ensure that the Ethernet module is out of reset */
reset = readl(AM3517_IP_SW_RESET);
reset &= (~CPGMACSS_SW_RST);
writel(reset, AM3517_IP_SW_RESET);
return 0;
}
@ -169,12 +138,6 @@ void set_muxconf_regs(void)
MUX_AM3517EVM();
}
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
int board_eth_init(bd_t *bis)

26
board/logicpd/am3517evm/am3517evm.h
View File

@ -111,7 +111,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) \
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
@ -339,18 +339,18 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
/* ETK (ES2 onwards) */\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \

19
board/logicpd/omap3som/omap3logic.h
View File

@ -161,12 +161,14 @@ void set_muxconf_regs(void)
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
#ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
#endif
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
@ -231,6 +233,23 @@ void set_muxconf_regs(void)
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
#ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA0*/
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA1*/
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*HSUSB2_DATA2*/
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*HSUSB2_DATA3*/
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA4*/
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_NXT*/
#endif
}
#endif

55
board/ti/j721e/Kconfig Normal file
View File

@ -0,0 +1,55 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
choice
prompt "K3 J721E based boards"
optional
config TARGET_J721E_A72_EVM
bool "TI K3 based J721E EVM running on A72"
select ARM64
select SOC_K3_J721E
select SYS_DISABLE_DCACHE_OPS
config TARGET_J721E_R5_EVM
bool "TI K3 based J721E EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select SOC_K3_J721E
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
imply SYS_K3_SPL_ATF
endchoice
if TARGET_J721E_A72_EVM
config SYS_BOARD
default "j721e"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "j721e_evm"
endif
if TARGET_J721E_R5_EVM
config SYS_BOARD
default "j721e"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "j721e_evm"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
endif

7
board/ti/j721e/MAINTAINERS Normal file
View File

@ -0,0 +1,7 @@
J721E BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
S: Maintained
F: board/ti/j721e
F: include/configs/j721e_evm.h
F: configs/j721e_evm_r5_defconfig
F: configs/j721e_evm_a72_defconfig

8
board/ti/j721e/Makefile Normal file
View File

@ -0,0 +1,8 @@
#
# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += evm.o

82
board/ti/j721e/evm.c Normal file
View File

@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board specific initialization for J721E EVM
*
* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
#include <common.h>
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
int dram_init(void)
{
#ifdef CONFIG_PHYS_64BIT
gd->ram_size = 0x100000000;
#else
gd->ram_size = 0x80000000;
#endif
return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
if (gd->ram_top > 0x100000000)
return 0x100000000;
#endif
return gd->ram_top;
}
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
return 0;
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (!strcmp(name, "k3-j721e-common-proc-board"))
return 0;
return -1;
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
int ret;
ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000");
if (ret)
printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
return ret;
}
#endif

42
cmd/remoteproc.c
View File

@ -34,6 +34,10 @@ static int print_remoteproc_list(void)
uc_pdata = dev_get_uclass_platdata(dev);
/* Do not print if rproc is not probed */
if (!(dev->flags & DM_FLAG_ACTIVATED))
continue;
switch (uc_pdata->mem_type) {
case RPROC_INTERNAL_MEMORY_MAPPED:
type = "internal memory mapped";
@ -68,12 +72,22 @@ static int print_remoteproc_list(void)
static int do_rproc_init(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
int id;
if (rproc_is_initialized()) {
printf("\tRemote Processors are already initialized\n");
} else {
return CMD_RET_FAILURE;
}
if (argc == 1) {
if (!rproc_init())
return 0;
printf("Few Remote Processors failed to be initalized\n");
printf("Few Remote Processors failed to be initialized\n");
} else if (argc == 2) {
id = (int)simple_strtoul(argv[1], NULL, 10);
if (!rproc_dev_init(id))
return 0;
printf("Remote Processor %d failed to be initialized\n", id);
}
return CMD_RET_FAILURE;
@ -91,11 +105,6 @@ static int do_rproc_init(cmd_tbl_t *cmdtp, int flag, int argc,
static int do_remoteproc_list(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
if (!rproc_is_initialized()) {
printf("\t Remote Processors is not initialized\n");
return CMD_RET_USAGE;
}
if (print_remoteproc_list())
return CMD_RET_FAILURE;
@ -130,11 +139,6 @@ static int do_remoteproc_load(cmd_tbl_t *cmdtp, int flag, int argc,
return CMD_RET_USAGE;
}
if (!rproc_is_initialized()) {
printf("\tRemote Processors are not initialized\n");
return CMD_RET_USAGE;
}
ret = rproc_load(id, addr, size);
printf("Load Remote Processor %d with data@addr=0x%08lx %lu bytes:%s\n",
id, addr, size, ret ? " Failed!" : " Success!");
@ -165,11 +169,6 @@ static int do_remoteproc_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
id = (int)simple_strtoul(argv[1], NULL, 10);
if (!rproc_is_initialized()) {
printf("\tRemote Processors are not initialized\n");
return CMD_RET_USAGE;
}
if (!strcmp(argv[0], "start")) {
ret = rproc_start(id);
} else if (!strcmp(argv[0], "stop")) {
@ -203,8 +202,10 @@ static int do_remoteproc_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
}
static cmd_tbl_t cmd_remoteproc_sub[] = {
U_BOOT_CMD_MKENT(init, 0, 1, do_rproc_init,
"Enumerate and initialize all processors", ""),
U_BOOT_CMD_MKENT(init, 1, 1, do_rproc_init,
"Enumerate and initialize the remote processor(s)",
"id - ID of the remote processor\n"
"If id is not passed, initialize all the remote processors"),
U_BOOT_CMD_MKENT(list, 0, 1, do_remoteproc_list,
"list remote processors", ""),
U_BOOT_CMD_MKENT(load, 5, 1, do_remoteproc_load,
@ -270,7 +271,8 @@ U_BOOT_CMD(rproc, 5, 1, do_remoteproc,
"\t\tNote: Services are dependent on the driver capability\n"
"\t\t 'list' command shows the capability of each device\n"
"\n\tSubcommands:\n"
"\tinit - Enumerate and initalize the remote processors\n"
"\tinit <id> - Enumerate and initalize the remote processor.\n"
"\t if id is not passed, initialize all the remote prcessors\n"
"\tlist - list available remote processors\n"
"\tload <id> [addr] [size]- Load the remote processor with binary\n"
"\t image stored at address [addr] in memory\n"

23
configs/am3517_evm_defconfig
View File

@ -1,11 +1,15 @@
CONFIG_ARM=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_TPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
# CONFIG_TPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_AM3517_EVM=y
CONFIG_EMIF4=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
@ -14,9 +18,13 @@ CONFIG_BOOTDELAY=10
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_SPL_POWER_SUPPORT is not set
CONFIG_SYS_PROMPT="AM3517_EVM # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
@ -34,9 +42,13 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1920k(u-boot),256k(u-boot-env),8m(kernel),512k(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am3517-evm"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_PCA953X=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
@ -49,8 +61,12 @@ CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_TWL4030_POWER is not set
CONFIG_CONS_INDEX=3
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
@ -60,3 +76,4 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_AM35X=y
CONFIG_BCH=y
CONFIG_SPL_TINY_MEMSET=y

1
configs/am65x_evm_a53_defconfig
View File

@ -80,7 +80,6 @@ CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_K3=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y

2
configs/am65x_evm_r5_defconfig
View File

@ -86,7 +86,7 @@ CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_K3=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y

1
configs/am65x_hs_evm_a53_defconfig
View File

@ -77,7 +77,6 @@ CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_K3=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y

2
configs/am65x_hs_evm_r5_defconfig
View File

@ -86,7 +86,7 @@ CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_K3=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y

6
configs/da850_am18xxevm_defconfig
View File

@ -58,4 +58,10 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_DA8XX=y
CONFIG_USB_STORAGE=y
# CONFIG_FAT_WRITE is not set

1
configs/da850evm_defconfig
View File

@ -74,5 +74,6 @@ CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_DA8XX=y
CONFIG_USB_STORAGE=y
# CONFIG_FAT_WRITE is not set
CONFIG_USE_TINY_PRINTF=y

6
configs/da850evm_direct_nor_defconfig
View File

@ -61,3 +61,9 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_DA8XX=y
CONFIG_USB_STORAGE=y

6
configs/da850evm_nand_defconfig
View File

@ -67,5 +67,11 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_DA8XX=y
CONFIG_USB_STORAGE=y
# CONFIG_FAT_WRITE is not set
CONFIG_USE_TINY_PRINTF=y

86
configs/j721e_evm_a72_defconfig Normal file
View File

@ -0,0 +1,86 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_OF_LIBFDT_OVERLAY=y

95
configs/j721e_evm_r5_defconfig Normal file
View File

@ -0,0 +1,95 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DOS_PARTITION=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MISC=y
CONFIG_FS_LOADER=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384

2
configs/omap35_logic_defconfig
View File

@ -41,7 +41,6 @@ CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
@ -69,6 +68,7 @@ CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_OMAP is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y

2
configs/omap3_logic_defconfig
View File

@ -40,7 +40,6 @@ CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
@ -68,6 +67,7 @@ CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_OMAP is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y

11
doc/device-tree-bindings/power/ti,sci-pm-domain.txt
View File

@ -17,8 +17,15 @@ child of the sysfw node.
Required Properties:
--------------------
- compatible: Must be "ti,sci-pm-domain"
- #power-domain-cells: Must be 1 so that an id can be provided in each
device node.
- #power-domain-cells: Can be one of the following:
1: Containing the device id of each node
2: First entry should be device id
Second entry should be one of the floowing:
TI_SCI_PD_EXCLUSIVE: To allow device to be
exclusively controlled by
the requesting hosts.
TI_SCI_PD_SHARED: To allow device to be shared
by multiple hosts.
Example (AM65x):
----------------

291
drivers/firmware/ti_sci.c
View File

@ -87,11 +87,18 @@ struct ti_sci_info {
struct mbox_chan chan_notify;
struct ti_sci_xfer xfer;
struct list_head list;
struct list_head dev_list;
bool is_secure;
u8 host_id;
u8 seq;
};
struct ti_sci_exclusive_dev {
u32 id;
u32 count;
struct list_head list;
};
#define handle_to_ti_sci_info(h) container_of(h, struct ti_sci_info, handle)
/**
@ -101,7 +108,8 @@ struct ti_sci_info {
* @msg_flags: Flag to set for the message
* @buf: Buffer to be send to mailbox channel
* @tx_message_size: transmit message size
* @rx_message_size: receive message size
* @rx_message_size: receive message size. may be set to zero for send-only
* transactions.
*
* Helper function which is used by various command functions that are
* exposed to clients of this driver for allocating a message traffic event.
@ -121,7 +129,8 @@ static struct ti_sci_xfer *ti_sci_setup_one_xfer(struct ti_sci_info *info,
/* Ensure we have sane transfer sizes */
if (rx_message_size > info->desc->max_msg_size ||
tx_message_size > info->desc->max_msg_size ||
rx_message_size < sizeof(*hdr) || tx_message_size < sizeof(*hdr))
(rx_message_size > 0 && rx_message_size < sizeof(*hdr)) ||
tx_message_size < sizeof(*hdr))
return ERR_PTR(-ERANGE);
info->seq = ~info->seq;
@ -219,7 +228,9 @@ static inline int ti_sci_do_xfer(struct ti_sci_info *info,
xfer->tx_message.buf = (u32 *)secure_buf;
xfer->tx_message.len += sizeof(secure_hdr);
xfer->rx_len += sizeof(secure_hdr);
if (xfer->rx_len)
xfer->rx_len += sizeof(secure_hdr);
}
/* Send the message */
@ -230,7 +241,11 @@ static inline int ti_sci_do_xfer(struct ti_sci_info *info,
return ret;
}
return ti_sci_get_response(info, xfer, &info->chan_rx);
/* Get response if requested */
if (xfer->rx_len)
ret = ti_sci_get_response(info, xfer, &info->chan_rx);
return ret;
}
/**
@ -419,6 +434,47 @@ static int ti_sci_cmd_set_board_config_pm(const struct ti_sci_handle *handle,
addr, size);
}
static struct ti_sci_exclusive_dev
*ti_sci_get_exclusive_dev(struct list_head *dev_list, u32 id)
{
struct ti_sci_exclusive_dev *dev;
list_for_each_entry(dev, dev_list, list)
if (dev->id == id)
return dev;
return NULL;
}
static void ti_sci_add_exclusive_dev(struct ti_sci_info *info, u32 id)
{
struct ti_sci_exclusive_dev *dev;
dev = ti_sci_get_exclusive_dev(&info->dev_list, id);
if (dev) {
dev->count++;
return;
}
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
dev->id = id;
dev->count = 1;
INIT_LIST_HEAD(&dev->list);
list_add_tail(&dev->list, &info->dev_list);
}
static void ti_sci_delete_exclusive_dev(struct ti_sci_info *info, u32 id)
{
struct ti_sci_exclusive_dev *dev;
dev = ti_sci_get_exclusive_dev(&info->dev_list, id);
if (!dev)
return;
if (dev->count > 0)
dev->count--;
}
/**
* ti_sci_set_device_state() - Set device state helper
* @handle: pointer to TI SCI handle
@ -466,6 +522,54 @@ static int ti_sci_set_device_state(const struct ti_sci_handle *handle,
if (!ti_sci_is_response_ack(resp))
return -ENODEV;
if (state == MSG_DEVICE_SW_STATE_AUTO_OFF)
ti_sci_delete_exclusive_dev(info, id);
else if (flags & MSG_FLAG_DEVICE_EXCLUSIVE)
ti_sci_add_exclusive_dev(info, id);
return ret;
}
/**
* ti_sci_set_device_state_no_wait() - Set device state helper without
* requesting or waiting for a response.
* @handle: pointer to TI SCI handle
* @id: Device identifier
* @flags: flags to setup for the device
* @state: State to move the device to
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_set_device_state_no_wait(const struct ti_sci_handle *handle,
u32 id, u32 flags, u8 state)
{
struct ti_sci_msg_req_set_device_state req;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_SET_DEVICE_STATE,
flags | TI_SCI_FLAG_REQ_GENERIC_NORESPONSE,
(u32 *)&req, sizeof(req), 0);
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.id = id;
req.state = state;
ret = ti_sci_do_xfer(info, xfer);
if (ret)
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
@ -547,8 +651,14 @@ static int ti_sci_get_device_state(const struct ti_sci_handle *handle,
*/
static int ti_sci_cmd_get_device(const struct ti_sci_handle *handle, u32 id)
{
return ti_sci_set_device_state(handle, id,
MSG_FLAG_DEVICE_EXCLUSIVE,
return ti_sci_set_device_state(handle, id, 0,
MSG_DEVICE_SW_STATE_ON);
}
static int ti_sci_cmd_get_device_exclusive(const struct ti_sci_handle *handle,
u32 id)
{
return ti_sci_set_device_state(handle, id, MSG_FLAG_DEVICE_EXCLUSIVE,
MSG_DEVICE_SW_STATE_ON);
}
@ -566,7 +676,14 @@ static int ti_sci_cmd_get_device(const struct ti_sci_handle *handle, u32 id)
static int ti_sci_cmd_idle_device(const struct ti_sci_handle *handle, u32 id)
{
return ti_sci_set_device_state(handle, id,
MSG_FLAG_DEVICE_EXCLUSIVE,
0,
MSG_DEVICE_SW_STATE_RETENTION);
}
static int ti_sci_cmd_idle_device_exclusive(const struct ti_sci_handle *handle,
u32 id)
{
return ti_sci_set_device_state(handle, id, MSG_FLAG_DEVICE_EXCLUSIVE,
MSG_DEVICE_SW_STATE_RETENTION);
}
@ -583,8 +700,27 @@ static int ti_sci_cmd_idle_device(const struct ti_sci_handle *handle, u32 id)
*/
static int ti_sci_cmd_put_device(const struct ti_sci_handle *handle, u32 id)
{
return ti_sci_set_device_state(handle, id,
0, MSG_DEVICE_SW_STATE_AUTO_OFF);
return ti_sci_set_device_state(handle, id, 0,
MSG_DEVICE_SW_STATE_AUTO_OFF);
}
static
int ti_sci_cmd_release_exclusive_devices(const struct ti_sci_handle *handle)
{
struct ti_sci_exclusive_dev *dev, *tmp;
struct ti_sci_info *info;
int i, cnt;
info = handle_to_ti_sci_info(handle);
list_for_each_entry_safe(dev, tmp, &info->dev_list, list) {
cnt = dev->count;
debug("%s: id = %d, cnt = %d\n", __func__, dev->id, cnt);
for (i = 0; i < cnt; i++)
ti_sci_cmd_put_device(handle, dev->id);
}
return 0;
}
/**
@ -2026,6 +2162,137 @@ static int ti_sci_cmd_get_proc_boot_status(const struct ti_sci_handle *handle,
return ret;
}
/**
* ti_sci_proc_wait_boot_status_no_wait() - Helper function to wait for a
* processor boot status without requesting or
* waiting for a response.
* @proc_id: Processor ID this request is for
* @num_wait_iterations: Total number of iterations we will check before
* we will timeout and give up
* @num_match_iterations: How many iterations should we have continued
* status to account for status bits glitching.
* This is to make sure that match occurs for
* consecutive checks. This implies that the
* worst case should consider that the stable
* time should at the worst be num_wait_iterations
* num_match_iterations to prevent timeout.
* @delay_per_iteration_us: Specifies how long to wait (in micro seconds)
* between each status checks. This is the minimum
* duration, and overhead of register reads and
* checks are on top of this and can vary based on
* varied conditions.
* @delay_before_iterations_us: Specifies how long to wait (in micro seconds)
* before the very first check in the first
* iteration of status check loop. This is the
* minimum duration, and overhead of register
* reads and checks are.
* @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
* status matching this field requested MUST be 1.
* @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
* bits matching this field requested MUST be 1.
* @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
* status matching this field requested MUST be 0.
* @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
* bits matching this field requested MUST be 0.
*
* Return: 0 if all goes well, else appropriate error message
*/
static int
ti_sci_proc_wait_boot_status_no_wait(const struct ti_sci_handle *handle,
u8 proc_id,
u8 num_wait_iterations,
u8 num_match_iterations,
u8 delay_per_iteration_us,
u8 delay_before_iterations_us,
u32 status_flags_1_set_all_wait,
u32 status_flags_1_set_any_wait,
u32 status_flags_1_clr_all_wait,
u32 status_flags_1_clr_any_wait)
{
struct ti_sci_msg_req_wait_proc_boot_status req;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_WAIT_PROC_BOOT_STATUS,
TI_SCI_FLAG_REQ_GENERIC_NORESPONSE,
(u32 *)&req, sizeof(req), 0);
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.processor_id = proc_id;
req.num_wait_iterations = num_wait_iterations;
req.num_match_iterations = num_match_iterations;
req.delay_per_iteration_us = delay_per_iteration_us;
req.delay_before_iterations_us = delay_before_iterations_us;
req.status_flags_1_set_all_wait = status_flags_1_set_all_wait;
req.status_flags_1_set_any_wait = status_flags_1_set_any_wait;
req.status_flags_1_clr_all_wait = status_flags_1_clr_all_wait;
req.status_flags_1_clr_any_wait = status_flags_1_clr_any_wait;
ret = ti_sci_do_xfer(info, xfer);
if (ret)
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
/**
* ti_sci_cmd_proc_shutdown_no_wait() - Command to shutdown a core without
* requesting or waiting for a response. Note that this API call
* should be followed by placing the respective processor into
* either WFE or WFI mode.
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_cmd_proc_shutdown_no_wait(const struct ti_sci_handle *handle,
u8 proc_id)
{
int ret;
/*
* Send the core boot status wait message waiting for either WFE or
* WFI without requesting or waiting for a TISCI response with the
* maximum wait time to give us the best chance to get to the WFE/WFI
* command that should follow the invocation of this API before the
* DMSC-internal processing of this command times out. Note that
* waiting for the R5 WFE/WFI flags will also work on an ARMV8 type
* core as the related flag bit positions are the same.
*/
ret = ti_sci_proc_wait_boot_status_no_wait(handle, proc_id,
U8_MAX, 100, U8_MAX, U8_MAX,
0, PROC_BOOT_STATUS_FLAG_R5_WFE | PROC_BOOT_STATUS_FLAG_R5_WFI,
0, 0);
if (ret) {
dev_err(info->dev, "Sending core %u wait message fail %d\n",
proc_id, ret);
return ret;
}
/*
* Release a processor managed by TISCI without requesting or waiting
* for a response.
*/
ret = ti_sci_set_device_state_no_wait(handle, proc_id, 0,
MSG_DEVICE_SW_STATE_AUTO_OFF);
if (ret)
dev_err(info->dev, "Sending core %u shutdown message fail %d\n",
proc_id, ret);
return ret;
}
/**
* ti_sci_cmd_ring_config() - configure RA ring
* @handle: pointer to TI SCI handle
@ -2632,7 +2899,9 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
bops->board_config_pm = ti_sci_cmd_set_board_config_pm;
dops->get_device = ti_sci_cmd_get_device;
dops->get_device_exclusive = ti_sci_cmd_get_device_exclusive;
dops->idle_device = ti_sci_cmd_idle_device;
dops->idle_device_exclusive = ti_sci_cmd_idle_device_exclusive;
dops->put_device = ti_sci_cmd_put_device;
dops->is_valid = ti_sci_cmd_dev_is_valid;
dops->get_context_loss_count = ti_sci_cmd_dev_get_clcnt;
@ -2642,6 +2911,7 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
dops->is_transitioning = ti_sci_cmd_dev_is_trans;
dops->set_device_resets = ti_sci_cmd_set_device_resets;
dops->get_device_resets = ti_sci_cmd_get_device_resets;
dops->release_exclusive_devices = ti_sci_cmd_release_exclusive_devices;
cops->get_clock = ti_sci_cmd_get_clock;
cops->idle_clock = ti_sci_cmd_idle_clock;
@ -2672,6 +2942,7 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
pops->set_proc_boot_ctrl = ti_sci_cmd_set_proc_boot_ctrl;
pops->proc_auth_boot_image = ti_sci_cmd_proc_auth_boot_image;
pops->get_proc_boot_status = ti_sci_cmd_get_proc_boot_status;
pops->proc_shutdown_no_wait = ti_sci_cmd_proc_shutdown_no_wait;
rops->config = ti_sci_cmd_ring_config;
rops->get_config = ti_sci_cmd_ring_get_config;
@ -2835,6 +3106,8 @@ static int ti_sci_probe(struct udevice *dev)
ret = ti_sci_cmd_get_revision(&info->handle);
INIT_LIST_HEAD(&info->dev_list);
return ret;
}

50
drivers/firmware/ti_sci.h
View File

@ -50,6 +50,7 @@
#define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
#define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
#define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
/* Resource Management Requests */
#define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
@ -772,6 +773,55 @@ struct ti_sci_msg_resp_get_proc_boot_status {
u32 status_flags;
} __packed;
/**
* struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor
* boot status
* @hdr: Generic Header
* @processor_id: ID of processor
* @num_wait_iterations: Total number of iterations we will check before
* we will timeout and give up
* @num_match_iterations: How many iterations should we have continued
* status to account for status bits glitching.
* This is to make sure that match occurs for
* consecutive checks. This implies that the
* worst case should consider that the stable
* time should at the worst be num_wait_iterations
* num_match_iterations to prevent timeout.
* @delay_per_iteration_us: Specifies how long to wait (in micro seconds)
* between each status checks. This is the minimum
* duration, and overhead of register reads and
* checks are on top of this and can vary based on
* varied conditions.
* @delay_before_iterations_us: Specifies how long to wait (in micro seconds)
* before the very first check in the first
* iteration of status check loop. This is the
* minimum duration, and overhead of register
* reads and checks are.
* @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
* status matching this field requested MUST be 1.
* @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
* bits matching this field requested MUST be 1.
* @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
* status matching this field requested MUST be 0.
* @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
* bits matching this field requested MUST be 0.
*
* Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate
* message, or NACK in case of inability to satisfy request.
*/
struct ti_sci_msg_req_wait_proc_boot_status {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
u8 num_wait_iterations;
u8 num_match_iterations;
u8 delay_per_iteration_us;
u8 delay_before_iterations_us;
u32 status_flags_1_set_all_wait;
u32 status_flags_1_set_any_wait;
u32 status_flags_1_clr_all_wait;
u32 status_flags_1_clr_any_wait;
} __packed;
/**
* struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
*

116
drivers/mmc/am654_sdhci.c
View File

@ -72,6 +72,8 @@ struct am654_sdhci_plat {
u32 otap_del_sel;
u32 trm_icp;
u32 drv_strength;
u32 flags;
#define DLL_PRESENT (1 << 0)
bool dll_on;
};
@ -162,6 +164,10 @@ const struct sdhci_ops am654_sdhci_ops = {
.set_control_reg = &am654_sdhci_set_control_reg,
};
const struct sdhci_ops j721e_4bit_sdhci_ops = {
.set_control_reg = &am654_sdhci_set_control_reg,
};
int am654_sdhci_init(struct am654_sdhci_plat *plat)
{
u32 ctl_cfg_2 = 0;
@ -172,25 +178,29 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat)
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
regmap_read(plat->base, PHY_STAT1, &val);
if (~val & CALDONE_MASK) {
/* Calibrate IO lines */
regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK, PDB_MASK);
ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
val & CALDONE_MASK, 1, 20);
if (ret)
return ret;
if (plat->flags & DLL_PRESENT) {
regmap_read(plat->base, PHY_STAT1, &val);
if (~val & CALDONE_MASK) {
/* Calibrate IO lines */
regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
PDB_MASK);
ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
val, val & CALDONE_MASK,
1, 20);
if (ret)
return ret;
}
/* Configure DLL TRIM */
mask = DLL_TRIM_ICP_MASK;
val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
/* Configure DLL driver strength */
mask |= DR_TY_MASK;
val |= plat->drv_strength << DR_TY_SHIFT;
regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
}
/* Configure DLL TRIM */
mask = DLL_TRIM_ICP_MASK;
val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
/* Configure DLL driver strength */
mask |= DR_TY_MASK;
val |= plat->drv_strength << DR_TY_SHIFT;
regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
/* Enable pins by setting IO mux to 0 */
regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
@ -245,7 +255,7 @@ static int am654_sdhci_probe(struct udevice *dev)
AM654_SDHCI_MIN_FREQ);
if (ret)
return ret;
host->ops = &am654_sdhci_ops;
host->ops = (struct sdhci_ops *)dev_get_driver_data(dev);
host->mmc->priv = host;
upriv->mmc = host->mmc;
@ -268,37 +278,44 @@ static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
host->ioaddr = (void *)dev_read_addr(dev);
plat->non_removable = dev_read_bool(dev, "non-removable");
ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
if (ret)
return ret;
if (device_is_compatible(dev, "ti,am654-sdhci-5.1") ||
device_is_compatible(dev, "ti,j721e-sdhci-8bit"))
plat->flags |= DLL_PRESENT;
ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel);
if (ret)
return ret;
ret = dev_read_u32(dev, "ti,driver-strength-ohm", &drv_strength);
if (ret)
return ret;
if (plat->flags & DLL_PRESENT) {
ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
if (ret)
return ret;
switch (drv_strength) {
case 50:
plat->drv_strength = DRIVER_STRENGTH_50_OHM;
break;
case 33:
plat->drv_strength = DRIVER_STRENGTH_33_OHM;
break;
case 66:
plat->drv_strength = DRIVER_STRENGTH_66_OHM;
break;
case 100:
plat->drv_strength = DRIVER_STRENGTH_100_OHM;
break;
case 40:
plat->drv_strength = DRIVER_STRENGTH_40_OHM;
break;
default:
dev_err(dev, "Invalid driver strength\n");
return -EINVAL;
ret = dev_read_u32(dev, "ti,driver-strength-ohm",
&drv_strength);
if (ret)
return ret;
switch (drv_strength) {
case 50:
plat->drv_strength = DRIVER_STRENGTH_50_OHM;
break;
case 33:
plat->drv_strength = DRIVER_STRENGTH_33_OHM;
break;
case 66:
plat->drv_strength = DRIVER_STRENGTH_66_OHM;
break;
case 100:
plat->drv_strength = DRIVER_STRENGTH_100_OHM;
break;
case 40:
plat->drv_strength = DRIVER_STRENGTH_40_OHM;
break;
default:
dev_err(dev, "Invalid driver strength\n");
return -EINVAL;
}
}
ret = mmc_of_parse(dev, cfg);
@ -316,7 +333,18 @@ static int am654_sdhci_bind(struct udevice *dev)
}
static const struct udevice_id am654_sdhci_ids[] = {
{ .compatible = "ti,am654-sdhci-5.1" },
{
.compatible = "ti,am654-sdhci-5.1",
.data = (ulong)&am654_sdhci_ops,
},
{
.compatible = "ti,j721e-sdhci-8bit",
.data = (ulong)&am654_sdhci_ops,
},
{
.compatible = "ti,j721e-sdhci-4bit",
.data = (ulong)&j721e_4bit_sdhci_ops,
},
{ }
};

31
drivers/power/domain/ti-sci-power-domain.c
View File

@ -13,6 +13,7 @@
#include <errno.h>
#include <power-domain-uclass.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/**
* struct ti_sci_power_domain_data - pm domain controller information structure
@ -56,11 +57,16 @@ static int ti_sci_power_domain_on(struct power_domain *pd)
struct ti_sci_power_domain_data *data = dev_get_priv(pd->dev);
const struct ti_sci_handle *sci = data->sci;
const struct ti_sci_dev_ops *dops = &sci->ops.dev_ops;
u8 flags = (uintptr_t)pd->priv;
int ret;
debug("%s(pd=%p)\n", __func__, pd);
ret = dops->get_device(sci, pd->id);
if (flags & TI_SCI_PD_EXCLUSIVE)
ret = dops->get_device_exclusive(sci, pd->id);
else
ret = dops->get_device(sci, pd->id);
if (ret)
dev_err(power_domain->dev, "%s: get_device failed (%d)\n",
__func__, ret);
@ -85,6 +91,28 @@ static int ti_sci_power_domain_off(struct power_domain *pd)
return ret;
}
static int ti_sci_power_domain_of_xlate(struct power_domain *pd,
struct ofnode_phandle_args *args)
{
u8 flags;
debug("%s(power_domain=%p)\n", __func__, pd);
if (args->args_count < 1) {
debug("Invalid args_count: %d\n", args->args_count);
return -EINVAL;
}
pd->id = args->args[0];
/* By default request for device exclusive */
flags = TI_SCI_PD_EXCLUSIVE;
if (args->args_count == 2)
flags = args->args[1] & TI_SCI_PD_EXCLUSIVE;
pd->priv = (void *)(uintptr_t)flags;
return 0;
}
static const struct udevice_id ti_sci_power_domain_of_match[] = {
{ .compatible = "ti,sci-pm-domain" },
{ /* sentinel */ }
@ -95,6 +123,7 @@ static struct power_domain_ops ti_sci_power_domain_ops = {
.free = ti_sci_power_domain_free,
.on = ti_sci_power_domain_on,
.off = ti_sci_power_domain_off,
.of_xlate = ti_sci_power_domain_of_xlate,
};
U_BOOT_DRIVER(ti_sci_pm_domains) = {

20
drivers/remoteproc/Kconfig
View File

@ -22,15 +22,6 @@ config K3_SYSTEM_CONTROLLER
help
Say 'y' here to add support for TI' K3 System Controller.
config REMOTEPROC_K3
bool "Support for TI's K3 based remoteproc driver"
select REMOTEPROC
depends on DM
depends on ARCH_K3
depends on OF_CONTROL
help
Say 'y' here to add support for TI' K3 remoteproc driver.
config REMOTEPROC_SANDBOX
bool "Support for Test processor for Sandbox"
select REMOTEPROC
@ -50,6 +41,17 @@ config REMOTEPROC_STM32_COPRO
Say 'y' here to add support for STM32 Cortex-M4 coprocessors via the
remoteproc framework.
config REMOTEPROC_TI_K3_ARM64
bool "Support for TI's K3 based ARM64 remoteproc driver"
select REMOTEPROC
depends on DM
depends on ARCH_K3
depends on OF_CONTROL
help
Say y here to support TI's ARM64 processor subsystems
on various TI K3 family of SoCs through the remote processor
framework.
config REMOTEPROC_TI_POWER
bool "Support for TI Power processor"
select REMOTEPROC

2
drivers/remoteproc/Makefile
View File

@ -8,7 +8,7 @@ obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o
# Remote proc drivers - Please keep this list alphabetically sorted.
obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o
obj-$(CONFIG_REMOTEPROC_K3) += k3_rproc.o
obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o

136
drivers/remoteproc/k3_rproc.c → drivers/remoteproc/ti_k3_arm64_rproc.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Texas Instruments' K3 Remoteproc driver
* Texas Instruments' K3 ARM64 Remoteproc driver
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
@ -16,6 +16,7 @@
#include <asm/io.h>
#include <power-domain.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include "ti_sci_proc.h"
#define INVALID_ID 0xffff
@ -23,68 +24,53 @@
#define GTC_CNTR_EN 0x3
/**
* struct k3_rproc_privdata - Structure representing Remote processor data.
* struct k3_arm64_privdata - Structure representing Remote processor data.
* @rproc_pwrdmn: rproc power domain data
* @rproc_rst: rproc reset control data
* @sci: Pointer to TISCI handle
* @tsp: TISCI processor control helper structure
* @gtc_base: Timer base address.
* @proc_id: TISCI processor ID
* @host_id: TISCI host id to which the processor gets assigned to.
*/
struct k3_rproc_privdata {
struct k3_arm64_privdata {
struct power_domain rproc_pwrdmn;
struct power_domain gtc_pwrdmn;
struct reset_ctl rproc_rst;
const struct ti_sci_handle *sci;
struct ti_sci_proc tsp;
void *gtc_base;
u16 proc_id;
u16 host_id;
};
/**
* k3_rproc_load() - Load up the Remote processor image
* k3_arm64_load() - Load up the Remote processor image
* @dev: rproc device pointer
* @addr: Address at which image is available
* @size: size of the image
*
* Return: 0 if all goes good, else appropriate error message.
*/
static int k3_rproc_load(struct udevice *dev, ulong addr, ulong size)
static int k3_arm64_load(struct udevice *dev, ulong addr, ulong size)
{
struct k3_rproc_privdata *rproc = dev_get_priv(dev);
const struct ti_sci_proc_ops *pops = &rproc->sci->ops.proc_ops;
struct k3_arm64_privdata *rproc = dev_get_priv(dev);
int ret;
dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
/* request for the processor */
ret = pops->proc_request(rproc->sci, rproc->proc_id);
if (ret) {
dev_err(dev, "Requesting processor failed %d\n", ret);
ret = ti_sci_proc_request(&rproc->tsp);
if (ret)
return ret;
}
ret = pops->set_proc_boot_cfg(rproc->sci, rproc->proc_id, addr, 0, 0);
if (ret) {
dev_err(dev, "set_proc_boot_cfg failed %d\n", ret);
return ret;
}
dev_dbg(dev, "%s: rproc successfully loaded\n", __func__);
return 0;
return ti_sci_proc_set_config(&rproc->tsp, addr, 0, 0);
}
/**
* k3_rproc_start() - Start the remote processor
* k3_arm64_start() - Start the remote processor
* @dev: rproc device pointer
*
* Return: 0 if all went ok, else return appropriate error
*/
static int k3_rproc_start(struct udevice *dev)
static int k3_arm64_start(struct udevice *dev)
{
struct k3_rproc_privdata *rproc = dev_get_priv(dev);
const struct ti_sci_proc_ops *pops = &rproc->sci->ops.proc_ops;
struct k3_arm64_privdata *rproc = dev_get_priv(dev);
int ret;
dev_dbg(dev, "%s\n", __func__);
@ -109,33 +95,16 @@ static int k3_rproc_start(struct udevice *dev)
return ret;
}
if (rproc->host_id != INVALID_ID) {
ret = pops->proc_handover(rproc->sci, rproc->proc_id,
rproc->host_id);
if (ret) {
dev_err(dev, "Handover processor failed %d\n", ret);
return ret;
}
} else {
ret = pops->proc_release(rproc->sci, rproc->proc_id);
if (ret) {
dev_err(dev, "Processor release failed %d\n", ret);
return ret;
}
}
dev_dbg(dev, "%s: rproc successfully started\n", __func__);
return 0;
return ti_sci_proc_release(&rproc->tsp);
}
/**
* k3_rproc_init() - Initialize the remote processor
* k3_arm64_init() - Initialize the remote processor
* @dev: rproc device pointer
*
* Return: 0 if all went ok, else return appropriate error
*/
static int k3_rproc_init(struct udevice *dev)
static int k3_arm64_init(struct udevice *dev)
{
dev_dbg(dev, "%s\n", __func__);
@ -145,12 +114,33 @@ static int k3_rproc_init(struct udevice *dev)
return 0;
}
static const struct dm_rproc_ops k3_rproc_ops = {
.init = k3_rproc_init,
.load = k3_rproc_load,
.start = k3_rproc_start,
static const struct dm_rproc_ops k3_arm64_ops = {
.init = k3_arm64_init,
.load = k3_arm64_load,
.start = k3_arm64_start,
};
static int ti_sci_proc_of_to_priv(struct udevice *dev, struct ti_sci_proc *tsp)
{
dev_dbg(dev, "%s\n", __func__);
tsp->sci = ti_sci_get_by_phandle(dev, "ti,sci");
if (IS_ERR(tsp->sci)) {
dev_err(dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci));
return PTR_ERR(tsp->sci);
}
tsp->proc_id = dev_read_u32_default(dev, "ti,sci-proc-id", INVALID_ID);
if (tsp->proc_id == INVALID_ID) {
dev_err(dev, "proc id not populated\n");
return -ENOENT;
}
tsp->host_id = dev_read_u32_default(dev, "ti,sci-host-id", INVALID_ID);
tsp->ops = &tsp->sci->ops.proc_ops;
return 0;
}
/**
* k3_of_to_priv() - generate private data from device tree
* @dev: corresponding k3 remote processor device
@ -158,8 +148,8 @@ static const struct dm_rproc_ops k3_rproc_ops = {
*
* Return: 0 if all goes good, else appropriate error message.
*/
static int k3_rproc_of_to_priv(struct udevice *dev,
struct k3_rproc_privdata *rproc)
static int k3_arm64_of_to_priv(struct udevice *dev,
struct k3_arm64_privdata *rproc)
{
int ret;
@ -183,11 +173,9 @@ static int k3_rproc_of_to_priv(struct udevice *dev,
return ret;
}
rproc->sci = ti_sci_get_by_phandle(dev, "ti,sci");
if (IS_ERR(rproc->sci)) {
dev_err(dev, "ti_sci get failed: %d\n", ret);
return PTR_ERR(rproc->sci);
}
ret = ti_sci_proc_of_to_priv(dev, &rproc->tsp);
if (ret)
return ret;
rproc->gtc_base = dev_read_addr_ptr(dev);
if (!rproc->gtc_base) {
@ -195,30 +183,25 @@ static int k3_rproc_of_to_priv(struct udevice *dev,
return -ENODEV;
}
rproc->proc_id = dev_read_u32_default(dev, "ti,sci-proc-id",
INVALID_ID);
rproc->host_id = dev_read_u32_default(dev, "ti,sci-host-id",
INVALID_ID);
return 0;
}
/**
* k3_rproc_probe() - Basic probe
* k3_arm64_probe() - Basic probe
* @dev: corresponding k3 remote processor device
*
* Return: 0 if all goes good, else appropriate error message.
*/
static int k3_rproc_probe(struct udevice *dev)
static int k3_arm64_probe(struct udevice *dev)
{
struct k3_rproc_privdata *priv;
struct k3_arm64_privdata *priv;
int ret;
dev_dbg(dev, "%s\n", __func__);
priv = dev_get_priv(dev);
ret = k3_rproc_of_to_priv(dev, priv);
ret = k3_arm64_of_to_priv(dev, priv);
if (ret) {
dev_dbg(dev, "%s: Probe failed with error %d\n", __func__, ret);
return ret;
@ -229,16 +212,17 @@ static int k3_rproc_probe(struct udevice *dev)
return 0;
}
static const struct udevice_id k3_rproc_ids[] = {
static const struct udevice_id k3_arm64_ids[] = {
{ .compatible = "ti,am654-arm64"},
{ .compatible = "ti,am654-rproc"},
{}
};
U_BOOT_DRIVER(k3_rproc) = {
.name = "k3_rproc",
.of_match = k3_rproc_ids,
U_BOOT_DRIVER(k3_arm64) = {
.name = "k3_arm64",
.of_match = k3_arm64_ids,
.id = UCLASS_REMOTEPROC,
.ops = &k3_rproc_ops,
.probe = k3_rproc_probe,
.priv_auto_alloc_size = sizeof(struct k3_rproc_privdata),
.ops = &k3_arm64_ops,
.probe = k3_arm64_probe,
.priv_auto_alloc_size = sizeof(struct k3_arm64_privdata),
};

121
drivers/remoteproc/ti_sci_proc.h Normal file
View File

@ -0,0 +1,121 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Texas Instruments TI-SCI Processor Controller Helper Functions
*
* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
* Suman Anna <s-anna@ti.com>
*/
#ifndef REMOTEPROC_TI_SCI_PROC_H
#define REMOTEPROC_TI_SCI_PROC_H
#define TISCI_INVALID_HOST 0xff
/**
* struct ti_sci_proc - structure representing a processor control client
* @sci: cached TI-SCI protocol handle
* @ops: cached TI-SCI proc ops
* @proc_id: processor id for the consumer remoteproc device
* @host_id: host id to pass the control over for this consumer remoteproc
* device
*/
struct ti_sci_proc {
const struct ti_sci_handle *sci;
const struct ti_sci_proc_ops *ops;
u8 proc_id;
u8 host_id;
};
static inline int ti_sci_proc_request(struct ti_sci_proc *tsp)
{
int ret;
debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
ret = tsp->ops->proc_request(tsp->sci, tsp->proc_id);
if (ret)
pr_err("ti-sci processor request failed: %d\n", ret);
return ret;
}
static inline int ti_sci_proc_release(struct ti_sci_proc *tsp)
{
int ret;
debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
if (tsp->host_id != TISCI_INVALID_HOST)
ret = tsp->ops->proc_handover(tsp->sci, tsp->proc_id,
tsp->host_id);
else
ret = tsp->ops->proc_release(tsp->sci, tsp->proc_id);
if (ret)
pr_err("ti-sci processor release failed: %d\n", ret);
return ret;
}
static inline int ti_sci_proc_handover(struct ti_sci_proc *tsp)
{
int ret;
debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
ret = tsp->ops->proc_handover(tsp->sci, tsp->proc_id, tsp->host_id);
if (ret)
pr_err("ti-sci processor handover of %d to %d failed: %d\n",
tsp->proc_id, tsp->host_id, ret);
return ret;
}
static inline int ti_sci_proc_get_status(struct ti_sci_proc *tsp,
u64 *boot_vector, u32 *cfg_flags,
u32 *ctrl_flags, u32 *status_flags)
{
int ret;
ret = tsp->ops->get_proc_boot_status(tsp->sci, tsp->proc_id,
boot_vector, cfg_flags, ctrl_flags,
status_flags);
if (ret)
pr_err("ti-sci processor get_status failed: %d\n", ret);
debug("%s: proc_id = %d, boot_vector = 0x%llx, cfg_flags = 0x%x, ctrl_flags = 0x%x, sts = 0x%x\n",
__func__, tsp->proc_id, *boot_vector, *cfg_flags, *ctrl_flags,
*status_flags);
return ret;
}
static inline int ti_sci_proc_set_config(struct ti_sci_proc *tsp,
u64 boot_vector,
u32 cfg_set, u32 cfg_clr)
{
int ret;
debug("%s: proc_id = %d, boot_vector = 0x%llx, cfg_set = 0x%x, cfg_clr = 0x%x\n",
__func__, tsp->proc_id, boot_vector, cfg_set, cfg_clr);
ret = tsp->ops->set_proc_boot_cfg(tsp->sci, tsp->proc_id, boot_vector,
cfg_set, cfg_clr);
if (ret)
pr_err("ti-sci processor set_config failed: %d\n", ret);
return ret;
}
static inline int ti_sci_proc_set_control(struct ti_sci_proc *tsp,
u32 ctrl_set, u32 ctrl_clr)
{
int ret;
debug("%s: proc_id = %d, ctrl_set = 0x%x, ctrl_clr = 0x%x\n", __func__,
tsp->proc_id, ctrl_set, ctrl_clr);
ret = tsp->ops->set_proc_boot_ctrl(tsp->sci, tsp->proc_id, ctrl_set,
ctrl_clr);
if (ret)
pr_err("ti-sci processor set_control failed: %d\n", ret);
return ret;
}
#endif /* REMOTEPROC_TI_SCI_PROC_H */

2
include/configs/am3517_evm.h
View File

@ -28,6 +28,8 @@
* Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
*/
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
#ifdef CONFIG_USB_MUSB_AM35X
#ifdef CONFIG_USB_MUSB_HOST

4
include/configs/am57xx_evm.h
View File

@ -22,7 +22,9 @@
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONSOLEDEV "ttyO2"
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONSOLEDEV "ttyS2"
#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */

12
include/configs/da850evm.h
View File

@ -18,14 +18,6 @@
#define CONFIG_USE_SPIFLASH
#endif
/*
* Disable DM_* for SPL build and can be re-enabled after adding
* DM support in SPL
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_I2C
#undef CONFIG_DM_I2C_COMPAT
#endif
/*
* SoC Configuration
*/
@ -268,12 +260,8 @@
#endif
/* USB Configs */
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "da850evm"
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */

4
include/configs/dra7xx_evm.h
View File

@ -26,9 +26,9 @@
#endif
#if (CONFIG_CONS_INDEX == 1)
#define CONSOLEDEV "ttyO0"
#define CONSOLEDEV "ttyS0"
#elif (CONFIG_CONS_INDEX == 3)
#define CONSOLEDEV "ttyO2"
#define CONSOLEDEV "ttyS2"
#endif
#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */

103
include/configs/j721e_evm.h Normal file
View File

@ -0,0 +1,103 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration header file for K3 J721E EVM
*
* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef __CONFIG_J721E_EVM_H
#define __CONFIG_J721E_EVM_H
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h>
#define CONFIG_ENV_SIZE (128 << 10)
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
/* SPL Loader Configuration */
#ifdef CONFIG_TARGET_J721E_A72_EVM
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x280000
#else
/*
* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
* possible (to allow the build to go through), as this directly affects
* our memory footprint. The less we use for BSS the more we have available
* for everything else.
*/
#define CONFIG_SPL_BSS_MAX_SIZE 0xA000
/*
* Link BSS to be within SPL in a dedicated region located near the top of
* the MCU SRAM, this way making it available also before relocation. Note
* that we are not using the actual top of the MCU SRAM as there is a memory
* location filled in by the boot ROM that we want to read out without any
* interference from the C context.
*/
#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
CONFIG_SPL_BSS_MAX_SIZE)
/* Set the stack right below the SPL BSS section */
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
/* Configure R5 SPL post-relocation malloc pool in DDR */
#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
#endif
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_CQSPI_REF_CLK 133333333
/* U-Boot general configuration */
#define EXTRA_ENV_J721E_BOARD_SETTINGS \
"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"findfdt=" \
"setenv fdtfile ${default_device_tree};" \
"setenv overlay_files ${name_overlays}\0" \
"loadaddr=0x80080000\0" \
"fdtaddr=0x82000000\0" \
"overlayaddr=0x83000000\0" \
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
/* U-Boot MMC-specific configuration */
#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
"boot=mmc\0" \
"mmcdev=1\0" \
"bootpart=1:2\0" \
"bootdir=/boot\0" \
"rd_spec=-\0" \
"init_mmc=run args_all args_mmc\0" \
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"get_overlay_mmc=" \
"fdt address ${fdtaddr};" \
"fdt resize 0x100000;" \
"for overlay in $overlay_files;" \
"do;" \
"load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \
"fdt apply ${overlayaddr};" \
"done;\0" \
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
"${bootdir}/${name_kern}\0"
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
EXTRA_ENV_J721E_BOARD_SETTINGS \
EXTRA_ENV_J721E_BOARD_SETTINGS_MMC
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
#endif /* __CONFIG_J721E_EVM_H */

4
include/configs/omap3_logic.h
View File

@ -30,6 +30,10 @@
/* I2C */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
#ifdef CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4
#endif
/* Board NAND Info. */
#ifdef CONFIG_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */

2
include/configs/omap5_uevm.h
View File

@ -53,7 +53,7 @@
/* USB Networking options */
#define CONSOLEDEV "ttyO2"
#define CONSOLEDEV "ttyS2"
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1

3
include/dt-bindings/pinctrl/k3.h
View File

@ -35,4 +35,7 @@
#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#endif

9
include/dt-bindings/soc/ti,sci_pm_domain.h Normal file
View File

@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
#define TI_SCI_PD_EXCLUSIVE 1
#define TI_SCI_PD_SHARED 0
#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */

2
include/environment/ti/boot.h
View File

@ -10,7 +10,7 @@
#define __TI_BOOT_H
#ifndef CONSOLEDEV
#define CONSOLEDEV "ttyO2"
#define CONSOLEDEV "ttyS2"
#endif
#define VBMETA_PART_SIZE (64 * 1024)

11
include/linux/soc/ti/ti_sci_protocol.h
View File

@ -105,6 +105,9 @@ struct ti_sci_board_ops {
* -reset_state: pointer to u32 which will retrieve resets
* Returns 0 for successful request, else returns
* corresponding error message.
* @release_exclusive_devices: Command to release all the exclusive devices
* attached to this host. This should be used very carefully
* and only at the end of execution of your software.
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
@ -117,7 +120,10 @@ struct ti_sci_board_ops {
*/
struct ti_sci_dev_ops {
int (*get_device)(const struct ti_sci_handle *handle, u32 id);
int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
u32 id);
int (*put_device)(const struct ti_sci_handle *handle, u32 id);
int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
int (*get_context_loss_count)(const struct ti_sci_handle *handle,
@ -134,6 +140,7 @@ struct ti_sci_dev_ops {
u32 reset_state);
int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
u32 *reset_state);
int (*release_exclusive_devices)(const struct ti_sci_handle *handle);
};
/**
@ -263,6 +270,8 @@ struct ti_sci_core_ops {
* @set_proc_boot_ctrl: Setup limited control flags in specific cases.
* @proc_auth_boot_image:
* @get_proc_boot_status: Get the state of physical processor
* @proc_shutdown_no_wait: Shutdown a core without requesting or waiting for a
* response.
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
@ -284,6 +293,8 @@ struct ti_sci_proc_ops {
int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
u32 *sts_flags);
int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle,
u8 pid);
};
#define TI_SCI_RING_MODE_RING (0)

15
include/power-domain.h
View File

@ -55,23 +55,12 @@ struct udevice;
*
* @dev: The device which implements the power domain.
* @id: The power domain ID within the provider.
*
* Currently, the power domain API assumes that a single integer ID is enough
* to identify and configure any power domain for any power domain provider. If
* this assumption becomes invalid in the future, the struct could be expanded
* to either (a) add more fields to allow power domain providers to store
* additional information, or (b) replace the id field with an opaque pointer,
* which the provider would dynamically allocate during its .of_xlate op, and
* process during is .request op. This may require the addition of an extra op
* to clean up the allocation.
* @priv: Private data corresponding to each power domain.
*/
struct power_domain {
struct udevice *dev;
/*
* Written by of_xlate. We assume a single id is enough for now. In the
* future, we might add more fields here.
*/
unsigned long id;
void *priv;
};
/**