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ARM: socfpga: Disable D cache in SPL

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The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Marek Vasut 2018-05-08 20:32:01 +02:00
parent dc3249b91b
commit 7544ad0303
2 changed files with 2 additions and 2 deletions
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2
arch/arm/mach-socfpga/spl_a10.c
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@ -77,6 +77,8 @@ void spl_board_init(void)
void board_init_f(ulong dummy) void board_init_f(ulong dummy)
{ {
dcache_disable();
socfpga_init_security_policies(); socfpga_init_security_policies();
socfpga_sdram_remap_zero(); socfpga_sdram_remap_zero();

2
include/configs/socfpga_arria10_socdk.h
View File

@ -15,8 +15,6 @@
/* /*
* U-Boot general configurations * U-Boot general configurations
*/ */
/* Cache options */
#define CONFIG_SYS_DCACHE_OFF
/* Memory configurations */ /* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 #define PHYS_SDRAM_1_SIZE 0x40000000