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Blackfin: support boards with no external memory

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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2009-11-09 19:38:23 -05:00
parent dbda2c65e5
commit 7527feef06
5 changed files with 60 additions and 19 deletions
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16
cpu/blackfin/initcode.c
View File

@ -538,10 +538,18 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
* self-refresh. So we have to pull it out before programming.
*/
#ifdef EBIU_RSTCTL
# ifdef CONFIG_EBIU_RSTCTL_VAL
bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
# endif
# ifdef CONFIG_EBIU_DDRCTL0_VAL
bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
# endif
# ifdef CONFIG_EBIU_DDRCTL1_VAL
bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
# endif
# ifdef CONFIG_EBIU_DDRCTL2_VAL
bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
# endif
# ifdef CONFIG_EBIU_DDRCTL3_VAL
/* default is disable, so don't need to force this */
bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
@ -611,11 +619,17 @@ program_async_controller(ADI_BOOT_DATA *bs)
serial_putc('b');
#ifdef EBIU_MODE
/* Not all parts have these additional MMRs. */
#ifdef EBIU_MODE
# ifdef CONFIG_EBIU_MBSCTL_VAL
bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
# endif
# ifdef CONFIG_EBIU_MODE_VAL
bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
# endif
# ifdef CONFIG_EBIU_FCTL_VAL
bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
# endif
#endif
serial_putc('c');

6
cpu/blackfin/start.S
View File

@ -95,6 +95,7 @@ ENTRY(_start)
/* Save RETX so we can pass it while booting Linux */
r7 = RETX;
#if CONFIG_MEM_SIZE
/* Figure out where we are currently executing so that we can decide
* how to best reprogram and relocate things. We'll pass below:
* R4: load address of _start
@ -131,6 +132,9 @@ ENTRY(_start)
r3.h = 0x2000;
cc = r5 < r3 (iu);
if cc jump .Ldma_and_reprogram;
#else
r6 = 1 (x); /* fake loaded_from_ldr = 1 */
#endif
r0 = 0 (x); /* set bootstruct to NULL */
call _initcode;
jump .Lprogrammed;
@ -154,6 +158,7 @@ ENTRY(_start)
.Lprogrammed:
serial_early_set_baud
#if CONFIG_MEM_SIZE
/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
* monitor location in the end of RAM. We know that memcpy() only
* uses registers, so it is safe to call here. Note that this only
@ -166,6 +171,7 @@ ENTRY(_start)
r2.l = LO(CONFIG_SYS_MONITOR_LEN);
r2.h = HI(CONFIG_SYS_MONITOR_LEN);
call _memcpy_ASM;
#endif
/* Initialize BSS section ... we know that memset() does not
* use the BSS, so it is safe to call here. The bootrom LDR

9
include/asm-blackfin/config.h
View File

@ -92,7 +92,11 @@
# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
# if CONFIG_SYS_MAX_RAM_SIZE
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
# else
# define CONFIG_SYS_MONITOR_BASE 0
# endif
#endif
#ifndef CONFIG_SYS_MALLOC_BASE
# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
@ -114,7 +118,8 @@
#endif
/* Check to make sure everything fits in external RAM */
#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
#if CONFIG_SYS_MAX_RAM_SIZE && \
((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
# error Memory Map does not fit into configuration
#endif

27
lib_blackfin/board.c
View File

@ -130,17 +130,26 @@ void init_cplbtables(void)
dcplb_add(0xFF800000, L1_DMEMORY);
++i;
icplb_add(CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK, SDRAM_IKERNEL);
dcplb_add(CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK, SDRAM_DKERNEL);
++i;
if (CONFIG_MEM_SIZE) {
uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN;
mbase &= CPLB_PAGE_MASK;
mend &= CPLB_PAGE_MASK;
/* If the monitor crosses a 4 meg boundary, we'll need
* to lock two entries for it.
*/
if ((CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK) != ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK)) {
icplb_add((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK, SDRAM_IKERNEL);
dcplb_add((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK, SDRAM_DKERNEL);
icplb_add(mbase, SDRAM_IKERNEL);
dcplb_add(mbase, SDRAM_DKERNEL);
++i;
/*
* If the monitor crosses a 4 meg boundary, we'll need
* to lock two entries for it. We assume it doesn't
* cross two 4 meg boundaries ...
*/
if (mbase != mend) {
icplb_add(mend, SDRAM_IKERNEL);
dcplb_add(mend, SDRAM_DKERNEL);
++i;
}
}
icplb_add(0x20000000, SDRAM_INON_CHBL);

21
lib_blackfin/u-boot.lds.S
View File

@ -57,7 +57,14 @@ OUTPUT_ARCH(bfin)
MEMORY
{
#if CONFIG_MEM_SIZE
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
# define ram_code ram
# define ram_data ram
#else
# define ram_code l1_code
# define ram_data l1_data
#endif
l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
@ -82,7 +89,7 @@ SECTIONS
.text :
{
*(.text .text.*)
} >ram
} >ram_code
.rodata :
{
@ -91,7 +98,7 @@ SECTIONS
*(.rodata1)
*(.eh_frame)
. = ALIGN(4);
} >ram
} >ram_data
.data :
{
@ -102,14 +109,14 @@ SECTIONS
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
} >ram
} >ram_data
.u_boot_cmd :
{
___u_boot_cmd_start = .;
*(.u_boot_cmd)
___u_boot_cmd_end = .;
} >ram
} >ram_data
.text_l1 :
{
@ -118,7 +125,7 @@ SECTIONS
*(.l1.text)
. = ALIGN(4);
__etext_l1 = .;
} >l1_code AT>ram
} >l1_code AT>ram_code
__text_l1_lma = LOADADDR(.text_l1);
__text_l1_len = SIZEOF(.text_l1);
ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
@ -131,7 +138,7 @@ SECTIONS
*(.l1.bss)
. = ALIGN(4);
__edata_l1 = .;
} >l1_data AT>ram
} >l1_data AT>ram_data
__data_l1_lma = LOADADDR(.data_l1);
__data_l1_len = SIZEOF(.data_l1);
ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!")
@ -143,7 +150,7 @@ SECTIONS
*(.dynbss)
*(.bss .bss.*)
*(COMMON)
} >ram
} >ram_data
__bss_vma = ADDR(.bss);
__bss_len = SIZEOF(.bss);
}