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dm: powerpc: P1020: add i2c DM support

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This supports i2c DM for SoC P1020

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Biwen Li 2020-05-01 20:04:01 +08:00 committed by Priyanka Jain
parent d864f717bb
commit 74014dfcd8
4 changed files with 36 additions and 3 deletions
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2
arch/powerpc/dts/p1020-post.dtsi
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@ -44,6 +44,8 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
}; };
/* PCIe controller base address 0x9000 */ /* PCIe controller base address 0x9000 */

24
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
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@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/ */
#include <common.h> #include <common.h>
@ -227,6 +228,7 @@ int checkboard(void)
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u8 in, out, io_config, val; u8 in, out, io_config, val;
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME, printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
in_8(&cpld_data->cpld_rev_major) & 0x0F, in_8(&cpld_data->cpld_rev_major) & 0x0F,
@ -234,7 +236,26 @@ int checkboard(void)
in_8(&cpld_data->pcba_rev) & 0x0F); in_8(&cpld_data->pcba_rev) & 0x0F);
/* Initialize i2c early for rom_loc and flash bank information */ /* Initialize i2c early for rom_loc and flash bank information */
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); #if defined(CONFIG_DM_I2C)
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return -ENXIO;
}
if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
dm_i2c_read(dev, 1, &out, 1) < 0 ||
dm_i2c_read(dev, 3, &io_config, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
}
#else /* Non DM I2C support - will be removed */
i2c_set_bus_num(bus_num);
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
@ -242,6 +263,7 @@ int checkboard(void)
printf("Error reading i2c boot information!\n"); printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */ return 0; /* Don't want to hang() on this error */
} }
#endif
val = (in & io_config) | (out & (~io_config)); val = (in & io_config) | (out & (~io_config));

4
include/configs/P1022DS.h
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@ -359,8 +359,8 @@
#endif #endif
/* I2C */ /* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
@ -368,6 +368,8 @@
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
#endif
#define CONFIG_SYS_I2C_FSL
/* /*
* I2C2 EEPROM * I2C2 EEPROM

9
include/configs/p1_p2_rdb_pc.h
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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: GPL-2.0+ */
/* /*
* Copyright 2010-2011 Freescale Semiconductor, Inc. * Copyright 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/ */
/* /*
@ -537,8 +538,8 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */ /* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
@ -546,6 +547,12 @@
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */