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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

Browse Source 
Beside some rather unexciting sync of the DTs from the kernel tree, and
some Kconfig cleanup, there are some improvements for the ARMv5 Allwinner
family, to support boards with the F1C200s (64MB DRAM) better. We will
get actual board support as soon as the DTs have passed the Linux review
process.
There is also support for the X96 Mate TV Box, featuring the H616 SoC and
a full 4GB of DRAM.
Also we found the secret to enable SPI booting on the H616 (pin PC5 must
be pulled to GND), so the SPI boot support patch is now good to go.

Passed the gitlab CI, plus briefly tested on Pine64-LTS, LicheePi Nano,
X96 Mate and OrangePi Zero.
This commit is contained in:
Tom Rini 2022-10-20 08:58:05 -04:00
commit 73ceadcd72
230 changed files with 657 additions and 1037 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Kconfig
View File

@ -312,9 +312,9 @@ config SYS_MALLOC_LEN
default 0x4000000 if SANDBOX
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
default 0x200000 if ARCH_BMIPS || X86
default 0x120000 if MACH_SUNIV
default 0x220000 if MACH_SUN8I_V3S
default 0x4020000 if ARCH_SUNXI
default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256
default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64
default 0x120000 if SUNXI_MINIMUM_DRAM_MB >= 32
default 0x400000
help
This defines memory to be allocated for Dynamic allocation

3
arch/arm/dts/Makefile
View File

@ -713,7 +713,8 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-tanix-tx6.dtb \
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb
sun50i-h616-orangepi-zero2.dtb \
sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
sun50i-a64-bananapi-m64.dtb \

40
arch/arm/dts/sun4i-a10-inet9f-rev03.dts
View File

@ -63,7 +63,7 @@
compatible = "gpio-keys-polled";
poll-interval = <20>;
left-joystick-left {
event-left-joystick-left {
label = "Left Joystick Left";
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
@ -71,7 +71,7 @@
gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
};
left-joystick-right {
event-left-joystick-right {
label = "Left Joystick Right";
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
@ -79,7 +79,7 @@
gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
};
left-joystick-up {
event-left-joystick-up {
label = "Left Joystick Up";
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
@ -87,7 +87,7 @@
gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
};
left-joystick-down {
event-left-joystick-down {
label = "Left Joystick Down";
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
@ -95,7 +95,7 @@
gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
};
right-joystick-left {
event-right-joystick-left {
label = "Right Joystick Left";
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
@ -103,7 +103,7 @@
gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
};
right-joystick-right {
event-right-joystick-right {
label = "Right Joystick Right";
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
@ -111,7 +111,7 @@
gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
};
right-joystick-up {
event-right-joystick-up {
label = "Right Joystick Up";
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
@ -119,7 +119,7 @@
gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
};
right-joystick-down {
event-right-joystick-down {
label = "Right Joystick Down";
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
@ -127,7 +127,7 @@
gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
};
dpad-left {
event-dpad-left {
label = "DPad Left";
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
@ -135,7 +135,7 @@
gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
};
dpad-right {
event-dpad-right {
label = "DPad Right";
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
@ -143,7 +143,7 @@
gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
};
dpad-up {
event-dpad-up {
label = "DPad Up";
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
@ -151,7 +151,7 @@
gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
};
dpad-down {
event-dpad-down {
label = "DPad Down";
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
@ -159,49 +159,49 @@
gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
};
x {
event-x {
label = "Button X";
linux,code = <BTN_X>;
gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
};
y {
event-y {
label = "Button Y";
linux,code = <BTN_Y>;
gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
};
a {
event-a {
label = "Button A";
linux,code = <BTN_A>;
gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
};
b {
event-b {
label = "Button B";
linux,code = <BTN_B>;
gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
};
select {
event-select {
label = "Select Button";
linux,code = <BTN_SELECT>;
gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
};
start {
event-start {
label = "Start Button";
linux,code = <BTN_START>;
gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
};
top-left {
event-top-left {
label = "Top Left Button";
linux,code = <BTN_TL>;
gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
};
top-right {
event-top-right {
label = "Top Right Button";
linux,code = <BTN_TR>;
gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */

6
arch/arm/dts/sun4i-a10-pcduino.dts
View File

@ -77,19 +77,19 @@
gpio-keys {
compatible = "gpio-keys";
back {
key-back {
label = "Key Back";
linux,code = <KEY_BACK>;
gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
};
home {
key-home {
label = "Key Home";
linux,code = <KEY_HOME>;
gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
};
menu {
key-menu {
label = "Key Menu";
linux,code = <KEY_MENU>;
gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;

2
arch/arm/dts/sun50i-a64-amarula-relic.dts
View File

@ -58,7 +58,7 @@
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
};

4
arch/arm/dts/sun50i-a64-bananapi-m64.dts
View File

@ -56,7 +56,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -355,7 +355,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_dldo2>;
vddio-supply = <&reg_dldo4>;

2
arch/arm/dts/sun50i-a64-nanopi-a64.dts
View File

@ -43,7 +43,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};

30
arch/arm/dts/sun50i-a64-olinuxino.dts
View File

@ -58,6 +58,15 @@
};
};
&codec {
status = "okay";
};
&codec_analog {
cpvdd-supply = <&reg_eldo1>;
status = "okay";
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
@ -74,6 +83,10 @@
cpu-supply = <&reg_dcdc2>;
};
&dai {
status = "okay";
};
&de {
status = "okay";
};
@ -328,6 +341,23 @@
vcc-hdmi-supply = <&reg_dldo1>;
};
&sound {
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,widgets = "Microphone", "Microphone Jack Left",
"Microphone", "Microphone Jack Right",
"Headphone", "Headphone Jack";
simple-audio-card,routing = "Left DAC", "DACL",
"Right DAC", "DACR",
"Headphone Jack", "HP",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"Microphone Jack Left", "MBIAS",
"MIC1", "Microphone Jack Left",
"Microphone Jack Right", "MBIAS",
"MIC2", "Microphone Jack Right";
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;

6
arch/arm/dts/sun50i-a64-orangepi-win.dts
View File

@ -40,7 +40,7 @@
leds {
compatible = "gpio-leds";
status {
led-0 {
label = "orangepi:green:status";
gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
};
@ -71,7 +71,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -369,7 +369,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <1500000>;
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_dldo2>;
vddio-supply = <&reg_dldo4>;

4
arch/arm/dts/sun50i-a64-pinebook.dts
View File

@ -35,10 +35,10 @@
stdout-path = "serial0:115200n8";
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
lid_switch {
lid-switch {
label = "Lid Switch";
gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
linux,input-type = <EV_SW>;

4
arch/arm/dts/sun50i-a64-pinephone-1.0.dts
View File

@ -10,6 +10,10 @@
compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64";
};
&codec_analog {
allwinner,internal-bias-resistor;
};
&sgm3140 {
enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */

4
arch/arm/dts/sun50i-a64-pinephone-1.1.dts
View File

@ -29,6 +29,10 @@
default-brightness-level = <400>;
};
&codec_analog {
allwinner,internal-bias-resistor;
};
&sgm3140 {
enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */

8
arch/arm/dts/sun50i-a64-teres-i.dts
View File

@ -197,6 +197,14 @@
status = "okay";
};
&pio {
vcc-pc-supply = <&reg_dcdc1>;
vcc-pd-supply = <&reg_dldo2>;
vcc-pe-supply = <&reg_aldo1>;
vcc-pf-supply = <&reg_dcdc1>; /* No dedicated supply-pin for this */
vcc-pg-supply = <&reg_aldo2>;
};
&pwm {
status = "okay";
};

10
arch/arm/dts/sun50i-a64.dtsi
View File

@ -4,6 +4,7 @@
// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -660,7 +661,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun50i-a64-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -672,7 +673,8 @@
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@ -1224,7 +1226,7 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu CLK_HDMI>, <&rtc 0>;
<&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
@ -1284,7 +1286,7 @@
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;

4
arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
View File

@ -52,10 +52,10 @@
};
};
r-gpio-keys {
gpio-keys {
compatible = "gpio-keys";
reset {
key-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/sun50i-h5-orangepi-pc2.dts
View File

@ -54,10 +54,10 @@
};
};
r-gpio-keys {
gpio-keys {
compatible = "gpio-keys";
sw4 {
key-sw4 {
label = "sw4";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/sun50i-h5-orangepi-prime.dts
View File

@ -48,10 +48,10 @@
};
};
r-gpio-keys {
gpio-keys {
compatible = "gpio-keys";
sw4 {
key-sw4 {
label = "sw4";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/sun50i-h6-orangepi-3.dts
View File

@ -86,7 +86,7 @@
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
post-power-on-delay-ms = <200>;
@ -314,7 +314,7 @@
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */

4
arch/arm/dts/sun50i-h6-orangepi-lite2.dts
View File

@ -13,7 +13,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
post-power-on-delay-ms = <200>;
@ -64,7 +64,7 @@
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */

2
arch/arm/dts/sun50i-h6-tanix.dtsi
View File

@ -78,7 +78,7 @@
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
};

12
arch/arm/dts/sun50i-h6.dtsi
View File

@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
@ -237,7 +238,7 @@
ccu: clock@3001000 {
compatible = "allwinner,sun50i-h6-ccu";
reg = <0x03001000 0x1000>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -316,7 +317,7 @@
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@ -724,7 +725,7 @@
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_XHCI>,
<&ccu CLK_BUS_XHCI>,
<&rtc 0>;
<&rtc CLK_OSC32K>;
clock-names = "ref", "bus_early", "suspend";
resets = <&ccu RST_BUS_XHCI>;
/*
@ -929,7 +930,7 @@
r_ccu: clock@7010000 {
compatible = "allwinner,sun50i-h6-r-ccu";
reg = <0x07010000 0x400>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
@ -958,7 +959,8 @@
reg = <0x07022000 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;

55
arch/arm/dts/sun50i-h616-orangepi-zero2.dts
View File

@ -49,29 +49,8 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_vcc5v>;
enable-active-high;
gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
status = "okay";
};
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
/* USB 2 & 3 are on headers only. */
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
@ -97,14 +76,6 @@
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&r_rsb {
status = "okay";
@ -181,14 +152,14 @@
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdcc: dcdcc {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
@ -200,7 +171,7 @@
};
reg_dcdce: dcdce {
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-eth-mmc";
@ -213,8 +184,18 @@
};
};
&pio {
vcc-pc-supply = <&reg_aldo1>;
vcc-pf-supply = <&reg_aldo1>;
vcc-pg-supply = <&reg_bldo1>;
vcc-ph-supply = <&reg_aldo1>;
vcc-pi-supply = <&reg_aldo1>;
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
flash@0 {
#address-cells = <1>;
@ -230,13 +211,3 @@
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

177
arch/arm/dts/sun50i-h616-x96-mate.dts Normal file
View File

@ -0,0 +1,177 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2021 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "X96 Mate";
compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the DC input */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&ir {
status = "okay";
};
&mmc0 {
vmmc-supply = <&reg_dcdce>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
status = "okay";
};
&mmc2 {
vmmc-supply = <&reg_dcdce>;
vqmmc-supply = <&reg_bldo1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
status = "okay";
};
&r_rsb {
status = "okay";
axp305: pmic@745 {
compatible = "x-powers,axp305", "x-powers,axp805",
"x-powers,axp806";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x745>;
x-powers,self-working-mode;
vina-supply = <&reg_vcc5v>;
vinb-supply = <&reg_vcc5v>;
vinc-supply = <&reg_vcc5v>;
vind-supply = <&reg_vcc5v>;
vine-supply = <&reg_vcc5v>;
aldoin-supply = <&reg_vcc5v>;
bldoin-supply = <&reg_vcc5v>;
cldoin-supply = <&reg_vcc5v>;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-sys";
};
/* Enabled by the Android BSP */
reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3-ext";
status = "disabled";
};
/* Enabled by the Android BSP */
reg_aldo3: aldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3-ext2";
status = "disabled";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8";
};
/* Enabled by the Android BSP */
reg_bldo2: bldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8-2";
status = "disabled";
};
bldo3 {
/* unused */
};
bldo4 {
/* unused */
};
cldo1 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5";
};
cldo2 {
/* unused */
};
cldo3 {
/* unused */
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdcc: dcdcc {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <1360000>;
regulator-max-microvolt = <1360000>;
regulator-name = "vdd-dram";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-eth-mmc";
};
sw {
/* unused */
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

286
arch/arm/dts/sun50i-h616.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h616-ccu.h>
#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/reset/sun50i-h616-ccu.h>
#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
@ -51,7 +52,23 @@
};
};
osc24M: osc24M_clk {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* 256 KiB reserved for Trusted Firmware-A (BL31).
* This is added by BL31 itself, but some bootloaders fail
* to propagate this into the DTB handed to kernels.
*/
secmon@40000000 {
reg = <0x0 0x40000000 0x0 0x40000>;
no-map;
};
};
osc24M: osc24M-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@ -110,7 +127,7 @@
ccu: clock@3001000 {
compatible = "allwinner,sun50i-h616-ccu";
reg = <0x03001000 0x1000>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -135,7 +152,7 @@
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@ -161,7 +178,7 @@
function = "i2c3";
};
ir_rx_pin: ir_rx_pin {
ir_rx_pin: ir-rx-pin {
pins = "PH10";
function = "ir_rx";
};
@ -174,6 +191,7 @@
bias-pull-up;
};
/omit-if-no-ref/
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
@ -191,17 +209,26 @@
bias-pull-up;
};
/omit-if-no-ref/
spi0_pins: spi0-pins {
pins = "PC0", "PC2", "PC3", "PC4";
pins = "PC0", "PC2", "PC4";
function = "spi0";
};
/omit-if-no-ref/
spi0_cs0_pin: spi0-cs0-pin {
pins = "PC3";
function = "spi0";
};
/omit-if-no-ref/
spi1_pins: spi1-pins {
pins = "PH6", "PH7", "PH8";
function = "spi1";
};
spi1_cs_pin: spi1-cs-pin {
/omit-if-no-ref/
spi1_cs0_pin: spi1-cs0-pin {
pins = "PH5";
function = "spi1";
};
@ -211,11 +238,13 @@
function = "uart0";
};
/omit-if-no-ref/
uart1_pins: uart1-pins {
pins = "PG6", "PG7";
function = "uart1";
};
/omit-if-no-ref/
uart1_rts_cts_pins: uart1-rts-cts-pins {
pins = "PG8", "PG9";
function = "uart1";
@ -245,10 +274,10 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "disabled";
max-frequency = <150000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-3_3v;
mmc-ddr-1_8v;
cap-sdio-irq;
#address-cells = <1>;
#size-cells = <0>;
@ -266,10 +295,10 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "disabled";
max-frequency = <150000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-3_3v;
mmc-ddr-1_8v;
cap-sdio-irq;
#address-cells = <1>;
#size-cells = <0>;
@ -287,10 +316,10 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
status = "disabled";
max-frequency = <150000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-3_3v;
mmc-ddr-1_8v;
cap-sdio-irq;
#address-cells = <1>;
#size-cells = <0>;
@ -364,6 +393,7 @@
i2c0: i2c@5002000 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002000 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@ -378,6 +408,7 @@
i2c1: i2c@5002400 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002400 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@ -390,6 +421,7 @@
i2c2: i2c@5002800 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002800 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@ -402,6 +434,7 @@
i2c3: i2c@5002c00 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002c00 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
@ -414,6 +447,7 @@
i2c4: i2c@5003000 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05003000 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@ -432,8 +466,6 @@
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_SPI0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -447,24 +479,22 @@
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_SPI1>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
emac0: ethernet@5020000 {
compatible = "allwinner,sun50i-h616-emac",
compatible = "allwinner,sun50i-h616-emac0",
"allwinner,sun50i-a64-emac";
syscon = <&syscon>;
reg = <0x05020000 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC0>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC0>;
clock-names = "stmmaceth";
resets = <&ccu RST_BUS_EMAC0>;
reset-names = "stmmaceth";
syscon = <&syscon>;
status = "disabled";
mdio0: mdio {
@ -474,197 +504,21 @@
};
};
emac1: ethernet@5030000 {
compatible = "allwinner,sun50i-h616-emac";
syscon = <&syscon 1>;
reg = <0x05030000 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC1>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC1>;
clock-names = "stmmaceth";
status = "disabled";
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
usbotg: usb@5100000 {
compatible = "allwinner,sun50i-h616-musb",
"allwinner,sun8i-h3-musb";
reg = <0x05100000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@5100400 {
compatible = "allwinner,sun50i-h616-usb-phy";
reg = <0x05100400 0x24>,
<0x05101800 0x14>,
<0x05200800 0x14>,
<0x05310800 0x14>,
<0x05311800 0x14>;
reg-names = "phy_ctrl",
"pmu0",
"pmu1",
"pmu2",
"pmu3";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>,
<&ccu CLK_USB_PHY2>,
<&ccu CLK_USB_PHY3>;
clock-names = "usb0_phy",
"usb1_phy",
"usb2_phy",
"usb3_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>,
<&ccu RST_USB_PHY2>,
<&ccu RST_USB_PHY3>;
reset-names = "usb0_reset",
"usb1_reset",
"usb2_reset",
"usb3_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci0: usb@5101000 {
compatible = "allwinner,sun50i-h616-ehci",
"generic-ehci";
reg = <0x05101000 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_BUS_EHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>,
<&ccu RST_BUS_EHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ohci0: usb@5101400 {
compatible = "allwinner,sun50i-h616-ohci",
"generic-ohci";
reg = <0x05101400 0x100>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ehci1: usb@5200000 {
compatible = "allwinner,sun50i-h616-ehci",
"generic-ehci";
reg = <0x05200000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_BUS_EHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>,
<&ccu RST_BUS_EHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@5200400 {
compatible = "allwinner,sun50i-h616-ohci",
"generic-ohci";
reg = <0x05200400 0x100>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ehci2: usb@5310000 {
compatible = "allwinner,sun50i-h616-ehci",
"generic-ehci";
reg = <0x05310000 0x100>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI2>,
<&ccu CLK_BUS_EHCI2>,
<&ccu CLK_USB_OHCI2>;
resets = <&ccu RST_BUS_OHCI2>,
<&ccu RST_BUS_EHCI2>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
ohci2: usb@5310400 {
compatible = "allwinner,sun50i-h616-ohci",
"generic-ohci";
reg = <0x05310400 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI2>,
<&ccu CLK_USB_OHCI2>;
resets = <&ccu RST_BUS_OHCI2>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
ehci3: usb@5311000 {
compatible = "allwinner,sun50i-h616-ehci",
"generic-ehci";
reg = <0x05311000 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI3>,
<&ccu CLK_BUS_EHCI3>,
<&ccu CLK_USB_OHCI3>;
resets = <&ccu RST_BUS_OHCI3>,
<&ccu RST_BUS_EHCI3>;
phys = <&usbphy 3>;
phy-names = "usb";
status = "disabled";
};
ohci3: usb@5311400 {
compatible = "allwinner,sun50i-h616-ohci",
"generic-ohci";
reg = <0x05311400 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI3>,
<&ccu CLK_USB_OHCI3>;
resets = <&ccu RST_BUS_OHCI3>;
phys = <&usbphy 3>;
phy-names = "usb";
status = "disabled";
};
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h616-rtc",
"allwinner,sun50i-h6-rtc";
compatible = "allwinner,sun50i-h616-rtc";
reg = <0x07000000 0x400>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k", "osc32k-out", "iosc";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
<&ccu CLK_PLL_SYSTEM_32K>;
clock-names = "bus", "hosc",
"pll-32k";
#clock-cells = <1>;
};
r_ccu: clock@7010000 {
compatible = "allwinner,sun50i-h616-r-ccu";
reg = <0x07010000 0x400>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
reg = <0x07010000 0x210>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
@ -674,14 +528,13 @@
r_pio: pinctrl@7022000 {
compatible = "allwinner,sun50i-h616-r-pinctrl";
reg = <0x07022000 0x400>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
/omit-if-no-ref/
r_i2c_pins: r-i2c-pins {
pins = "PL0", "PL1";
function = "s_i2c";
@ -694,21 +547,22 @@
};
ir: ir@7040000 {
compatible = "allwinner,sun50i-h616-ir",
"allwinner,sun6i-a31-ir";
reg = <0x07040000 0x400>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1_IR>,
<&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_R_APB1_IR>;
pinctrl-names = "default";
pinctrl-0 = <&ir_rx_pin>;
status = "disabled";
compatible = "allwinner,sun50i-h616-ir",
"allwinner,sun6i-a31-ir";
reg = <0x07040000 0x400>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1_IR>,
<&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_R_APB1_IR>;
pinctrl-names = "default";
pinctrl-0 = <&ir_rx_pin>;
status = "disabled";
};
r_i2c: i2c@7081400 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x07081400 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm/dts/sun5i-a13-licheepi-one.dts
View File

@ -67,18 +67,18 @@
compatible = "gpio-leds";
led-0 {
label ="licheepi:red:usr";
label = "licheepi:red:usr";
gpios = <&pio 2 5 GPIO_ACTIVE_LOW>;
};
led-1 {
label ="licheepi:green:usr";
label = "licheepi:green:usr";
gpios = <&pio 2 19 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-2 {
label ="licheepi:blue:usr";
label = "licheepi:blue:usr";
gpios = <&pio 2 4 GPIO_ACTIVE_LOW>;
};

13
arch/arm/dts/sun6i-a31.dtsi
View File

@ -46,6 +46,7 @@
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/clock/sun6i-a31-ccu.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
/ {
@ -598,7 +599,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun6i-a31-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -611,7 +612,8 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@ -1316,7 +1318,7 @@
ar100: ar100_clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
clocks = <&rtc 0>, <&osc24M>,
clocks = <&rtc CLK_OSC32K>, <&osc24M>,
<&ccu CLK_PLL_PERIPH>,
<&ccu CLK_PLL_PERIPH>;
clock-output-names = "ar100";
@ -1351,7 +1353,7 @@
ir_clk: ir_clk {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
clocks = <&rtc 0>, <&osc24M>;
clocks = <&rtc CLK_OSC32K>, <&osc24M>;
clock-output-names = "ir";
};
@ -1381,9 +1383,8 @@
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;

6
arch/arm/dts/sun7i-a20-pcduino3.dts
View File

@ -78,19 +78,19 @@
gpio-keys {
compatible = "gpio-keys";
back {
key-back {
label = "Key Back";
linux,code = <KEY_BACK>;
gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
};
home {
key-home {
label = "Key Home";
linux,code = <KEY_HOME>;
gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
};
menu {
key-menu {
label = "Key Menu";
linux,code = <KEY_MENU>;
gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;

9
arch/arm/dts/sun8i-a23-a33.dtsi
View File

@ -44,6 +44,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
@ -329,7 +330,7 @@
ccu: clock@1c20000 {
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -339,7 +340,8 @@
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c20800 0x400>;
/* interrupts get set in SoC specific dtsi file */
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@ -806,9 +808,8 @@
compatible = "allwinner,sun8i-a23-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;

73
arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts
View File

@ -1,73 +0,0 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-a23.dtsi"
#include "sun8i-q8-common.dtsi"
/ {
model = "Q8 A23 Tablet";
compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
};
&codec {
allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
allwinner,audio-routing =
"Headphone", "HP",
"Headphone", "HPCOM",
"Speaker", "HP",
"MIC1", "Mic",
"MIC2", "Headset Mic",
"Mic", "MBIAS",
"Headset Mic", "HBIAS";
status = "okay";
};
&panel {
compatible = "bananapi,s070wv20-ct16";
};
&tcon0_out {
tcon0_out_lcd: endpoint {
remote-endpoint = <&panel_input>;
};
};

1
arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts Symbolic link
View File

@ -0,0 +1 @@
sun8i-a23-q8-tablet.dts

73
arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts
View File

@ -1,73 +0,0 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-a23.dtsi"
#include "sun8i-q8-common.dtsi"
/ {
model = "Q8 A23 Tablet";
compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
};
&codec {
allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
allwinner,audio-routing =
"Headphone", "HP",
"Headphone", "HPCOM",
"Speaker", "HP",
"MIC1", "Mic",
"MIC2", "Headset Mic",
"Mic", "MBIAS",
"Headset Mic", "HBIAS";
status = "okay";
};
&panel {
compatible = "bananapi,s070wv20-ct16";
};
&tcon0_out {
tcon0_out_lcd: endpoint {
remote-endpoint = <&panel_input>;
};
};

1
arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts Symbolic link
View File

@ -0,0 +1 @@
sun8i-a23-q8-tablet.dts

57
arch/arm/dts/sun8i-a33-et-q8-v1.6.dts
View File

@ -1,57 +0,0 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-a33.dtsi"
#include "sun8i-q8-common.dtsi"
/ {
model = "Q8 A33 Tablet";
compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
};
&tcon0_out {
tcon0_out_lcd: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};

1
arch/arm/dts/sun8i-a33-et-q8-v1.6.dts Symbolic link
View File

@ -0,0 +1 @@
sun8i-a33-q8-tablet.dts

57
arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts
View File

@ -1,57 +0,0 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-a33.dtsi"
#include "sun8i-q8-common.dtsi"
/ {
model = "Q8 A33 Tablet";
compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
};
&tcon0_out {
tcon0_out_lcd: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};

1
arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts Symbolic link
View File

@ -0,0 +1 @@
sun8i-a33-q8-tablet.dts

8
arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
View File

@ -47,10 +47,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
sw4 {
switch-4 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@ -106,7 +106,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -181,7 +181,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <1500000>;
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

2
arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
View File

@ -169,7 +169,7 @@
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mxicy,mx25l1606e", "winbond,w25q128";
compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};

6
arch/arm/dts/sun8i-h3-beelink-x2.dts
View File

@ -93,10 +93,10 @@
};
};
r-gpio-keys {
gpio-keys {
compatible = "gpio-keys";
power {
key-power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@ -125,7 +125,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};

6
arch/arm/dts/sun8i-h3-mapleboard-mp130.dts
View File

@ -39,16 +39,16 @@
};
};
r_gpio_keys {
gpio-keys {
compatible = "gpio-keys";
power {
key-power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
};
user {
key-user {
label = "user";
linux,code = <BTN_0>;
gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;

8
arch/arm/dts/sun8i-h3-nanopi-duo2.dts
View File

@ -37,10 +37,10 @@
};
};
r_gpio_keys {
gpio-keys {
compatible = "gpio-keys";
k1 {
key-0 {
label = "k1";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
@ -90,7 +90,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
@ -151,7 +151,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

2
arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
View File

@ -127,7 +127,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

4
arch/arm/dts/sun8i-h3-nanopi-r1.dts
View File

@ -46,7 +46,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
@ -147,7 +147,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

5
arch/arm/dts/sun8i-h3-nanopi.dtsi
View File

@ -73,11 +73,10 @@
};
};
r_gpio_keys {
gpio-keys {
compatible = "gpio-keys";
input-name = "k1";
k1 {
key-0 {
label = "k1";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;

6
arch/arm/dts/sun8i-h3-orangepi-2.dts
View File

@ -88,16 +88,16 @@
};
};
r_gpio_keys {
gpio-keys {
compatible = "gpio-keys";
sw2 {
switch-2 {
label = "sw2";
linux,code = <BTN_1>;
gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
};
sw4 {
switch-4 {
label = "sw4";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/sun8i-h3-orangepi-lite.dts
View File

@ -87,10 +87,10 @@
};
};
r_gpio_keys {
gpio-keys {
compatible = "gpio-keys";
sw4 {
switch-4 {
label = "sw4";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/sun8i-h3-orangepi-one.dts
View File

@ -86,10 +86,10 @@
};
};
r_gpio_keys {
gpio-keys {
compatible = "gpio-keys";
sw4 {
switch-4 {
label = "sw4";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/sun8i-h3-orangepi-pc.dts
View File

@ -86,10 +86,10 @@
};
};
r_gpio_keys {
gpio-keys {
compatible = "gpio-keys";
sw4 {
switch-4 {
label = "sw4";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/sun8i-r16-bananapi-m2m.dts
View File

@ -91,7 +91,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -283,7 +283,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_dldo1>;
vddio-supply = <&reg_aldo3>;

5
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
View File

@ -43,6 +43,7 @@
/dts-v1/;
#include "sun8i-r40.dtsi"
#include "sun8i-r40-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@ -113,6 +114,10 @@
status = "okay";
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&de {
status = "okay";
};

52
arch/arm/dts/sun8i-r40-cpu-opp.dtsi Normal file
View File

@ -0,0 +1,52 @@
/{
cpu0_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1000000 1000000 1300000>;
clock-latency-ns = <2000000>;
};
opp-912000000 {
opp-hz = /bits/ 64 <912000000>;
opp-microvolt = <1100000 1100000 1300000>;
clock-latency-ns = <2000000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1160000 1160000 1300000>;
clock-latency-ns = <2000000>;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <1240000 1240000 1300000>;
clock-latency-ns = <2000000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1300000 1300000 1300000>;
clock-latency-ns = <2000000>;
};
};
};
&cpu0 {
operating-points-v2 = <&cpu0_opp_table>;
};
&cpu1 {
operating-points-v2 = <&cpu0_opp_table>;
};
&cpu2 {
operating-points-v2 = <&cpu0_opp_table>;
};
&cpu3 {
operating-points-v2 = <&cpu0_opp_table>;
};

5
arch/arm/dts/sun8i-r40-feta40i.dtsi
View File

@ -5,6 +5,11 @@
// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
#include "sun8i-r40.dtsi"
#include "sun8i-r40-cpu-opp.dtsi"
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&i2c0 {
status = "okay";

44
arch/arm/dts/sun8i-r40.dtsi
View File

@ -42,6 +42,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/clock/sun8i-tcon-top.h>
@ -84,24 +85,36 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clocks = <&ccu CLK_CPU>;
clock-names = "cpu";
#cooling-cells = <2>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
clocks = <&ccu CLK_CPU>;
clock-names = "cpu";
#cooling-cells = <2>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
clocks = <&ccu CLK_CPU>;
clock-names = "cpu";
#cooling-cells = <2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
clocks = <&ccu CLK_CPU>;
clock-names = "cpu";
#cooling-cells = <2>;
};
};
@ -117,6 +130,30 @@
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
trips {
cpu_hot_trip: cpu-hot {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_very_hot_trip: cpu-very-hot {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
cpu-hot-limit {
trip = <&cpu_hot_trip>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu_thermal: gpu-thermal {
@ -485,7 +522,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -504,7 +541,8 @@
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@ -1231,7 +1269,7 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
<&ccu CLK_HDMI>, <&rtc 0>;
<&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";

5
arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
View File

@ -45,6 +45,7 @@
/dts-v1/;
#include "sun8i-r40.dtsi"
#include "sun8i-r40-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@ -88,6 +89,10 @@
status = "okay";
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&de {
status = "okay";
};

6
arch/arm/dts/sun8i-v3s.dtsi
View File

@ -42,6 +42,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <dt-bindings/clock/sun8i-de2.h>
@ -321,7 +322,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -342,7 +343,8 @@
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;

5
arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
View File

@ -42,6 +42,7 @@
/dts-v1/;
#include "sun8i-r40.dtsi"
#include "sun8i-r40-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@ -107,6 +108,10 @@
status = "okay";
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&de {
status = "okay";
};

1
arch/arm/dts/sun9i-a80.dtsi
View File

@ -1218,7 +1218,6 @@
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
resets = <&apbs_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;

8
arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
View File

@ -77,10 +77,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
sw4 {
switch-4 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@ -101,7 +101,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -221,7 +221,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <1500000>;
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

4
arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi
View File

@ -22,7 +22,7 @@
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
post-power-on-delay-ms = <200>;
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -124,7 +124,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

13
arch/arm/dts/sunxi-h3-h5.dtsi
View File

@ -40,6 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
@ -386,7 +387,7 @@
ccu: clock@1c20000 {
/* compatible is in per SoC .dtsi file */
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -397,7 +398,8 @@
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@ -817,7 +819,7 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu CLK_HDMI>, <&rtc 0>;
<&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
@ -876,7 +878,7 @@
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-h3-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
@ -928,7 +930,8 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;

4
arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
View File

@ -42,10 +42,10 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
power {
key-power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */

16
arch/arm/mach-sunxi/Kconfig
View File

@ -185,6 +185,8 @@ config MACH_SUNIV
select CPU_ARM926EJS
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select SKIP_LOWLEVEL_INIT_ONLY
select SPL_SKIP_LOWLEVEL_INIT_ONLY
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
@ -615,6 +617,18 @@ config SYS_BOARD
config SYS_SOC
default "sunxi"
config SUNXI_MINIMUM_DRAM_MB
int "minimum DRAM size"
default 32 if MACH_SUNIV
default 64 if MACH_SUN8I_V3S
default 256
---help---
Minimum DRAM size expected on the board. Traditionally we assumed
256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM
we have smaller sizes, though, so that U-Boot's own load address and
the default payload addresses must be shifted down.
This is expected to be fixed by the SoC selection.
config UART0_PORT_F
bool "UART0 on MicroSD breakout board"
---help---
@ -998,7 +1012,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does

6
arch/arm/mach-sunxi/board.c
View File

@ -147,6 +147,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
@ -488,7 +492,7 @@ void reset_cpu(void)
}
#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

27
arch/arm/mach-sunxi/spl_spi_sunxi.c
View File

@ -78,7 +78,7 @@
#define CCM_AHB_GATING0 (0x01C20000 + 0x60)
#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c)
#ifdef CONFIG_MACH_SUN50I_H6
#ifdef CONFIG_SUN50I_GEN_H6
#define CCM_SPI0_CLK (0x03001000 + 0x940)
#else
#define CCM_SPI0_CLK (0x01C20000 + 0xA0)
@ -97,7 +97,7 @@
/*
* Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
* from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
* The H6 uses PC0, PC2, PC3, PC5.
* The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4.
*/
static void spi0_pinmux_setup(unsigned int pin_function)
{
@ -105,11 +105,14 @@ static void spi0_pinmux_setup(unsigned int pin_function)
sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
/* All chips except H6 use PC1, and only H6 uses PC5. */
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
/* All chips except H6 and H616 use PC1. */
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
else
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function);
/* Older generations use PC23 for CS, newer ones use PC3. */
if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
@ -122,7 +125,7 @@ static void spi0_pinmux_setup(unsigned int pin_function)
static bool is_sun6i_gen_spi(void)
{
return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6);
IS_ENABLED(CONFIG_SUN50I_GEN_H6);
}
static uintptr_t spi0_base_address(void)
@ -130,7 +133,7 @@ static uintptr_t spi0_base_address(void)
if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
return 0x01C05000;
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
return 0x05010000;
if (!is_sun6i_gen_spi() ||
@ -148,14 +151,14 @@ static void spi0_enable_clock(void)
uintptr_t base = spi0_base_address();
/* Deassert SPI0 reset on SUN6I */
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
else if (is_sun6i_gen_spi())
setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
(1 << AHB_RESET_SPI0_SHIFT));
/* Open the SPI0 gate */
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
@ -202,11 +205,11 @@ static void spi0_disable_clock(void)
writel(0, CCM_SPI0_CLK);
/* Close the SPI0 gate */
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Assert SPI0 reset on SUN6I */
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
else if (is_sun6i_gen_spi())
clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
@ -218,7 +221,7 @@ static void spi0_init(void)
unsigned int pin_function = SUNXI_GPC_SPI0;
if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6))
IS_ENABLED(CONFIG_SUN50I_GEN_H6))
pin_function = SUN50I_GPC_SPI0;
else if (IS_ENABLED(CONFIG_MACH_SUNIV))
pin_function = SUNIV_GPC_SPI0;

5
board/sunxi/MAINTAINERS
View File

@ -535,6 +535,11 @@ M: Aleksei Mamlin <mamlinav@gmail.com>
S: Maintained
F: configs/Wexler_TAB7200_defconfig
X96 MATE TV BOX
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
F: configs/x96_mate_defconfig
YONES TOPTECH BD1078 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained

4
boot/Kconfig
View File

@ -499,8 +499,8 @@ config SYS_TEXT_BASE
default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
default 0x81700000 if MACH_SUNIV
default 0x2a000000 if MACH_SUN9I
default 0x42e00000 if MACH_SUN8I_V3S
default 0x4a000000 if ARCH_SUNXI
default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
hex "Text Base"
help
The address in memory that U-Boot will be running from, initially.

1
cmd/Kconfig
View File

@ -86,6 +86,7 @@ config SYS_CBSIZE
config SYS_PBSIZE
int "Buffer size for console output"
default 1024 if ARCH_SUNXI
default 1044
config SYS_XTRACE

6
common/spl/Kconfig
View File

@ -81,6 +81,7 @@ config SPL_MAX_SIZE
default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
default 0xbfa0 if MACH_SUN50I_H616
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
default 0x10000 if ASPEED_AST2600
@ -353,6 +354,11 @@ config SPL_STACK
default 0x946bb8 if ARCH_MX7
default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x118000 if MACH_SUN50I_H6
default 0x58000 if MACH_SUN50I_H616
default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
default 0x18000 if MACH_SUN9I
default 0x8000 if ARCH_SUNXI
help
Address of the start of the stack SPL will use before SDRAM is
initialized.

2
configs/A10-OLinuXino-Lime_defconfig
View File

@ -11,9 +11,7 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/A10s-OLinuXino-M_defconfig
View File

@ -9,9 +9,7 @@ CONFIG_MMC1_CD_PIN="PG13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/A13-OLinuXinoM_defconfig
View File

@ -13,8 +13,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/A13-OLinuXino_defconfig
View File

@ -15,9 +15,7 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_DFU_RAM=y

2
configs/A20-OLinuXino-Lime2-eMMC_defconfig
View File

@ -13,9 +13,7 @@ CONFIG_SATAPWR="PC3"
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y

2
configs/A20-OLinuXino-Lime2_defconfig
View File

@ -11,9 +11,7 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y

2
configs/A20-OLinuXino-Lime_defconfig
View File

@ -9,9 +9,7 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/A20-OLinuXino_MICRO-eMMC_defconfig
View File

@ -11,9 +11,7 @@ CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/A20-OLinuXino_MICRO_defconfig
View File

@ -12,9 +12,7 @@ CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/A20-Olimex-SOM-EVB_defconfig
View File

@ -12,9 +12,7 @@ CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
View File

@ -13,9 +13,7 @@ CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y

2
configs/A20-Olimex-SOM204-EVB_defconfig
View File

@ -12,9 +12,7 @@ CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y

2
configs/A33-OLinuXino_defconfig
View File

@ -16,7 +16,5 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PB2"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SYS_PBSIZE=1024
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_USB_MUSB_HOST=y

2
configs/Ainol_AW1_defconfig
View File

@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/Ampe_A76_defconfig
View File

@ -15,9 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/Auxtek-T003_defconfig
View File

@ -8,9 +8,7 @@ CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/Auxtek-T004_defconfig
View File

@ -6,9 +6,7 @@ CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/Bananapi_M2_Ultra_defconfig
View File

@ -12,9 +12,7 @@ CONFIG_USB2_VBUS_PIN="PH23"
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/Bananapi_defconfig
View File

@ -9,9 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

2
configs/Bananapi_m2m_defconfig
View File

@ -10,8 +10,6 @@ CONFIG_MMC0_CD_PIN="PB4"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SYS_PBSIZE=1024
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

2
configs/Bananapro_defconfig
View File

@ -11,9 +11,7 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

2
configs/CHIP_defconfig
View File

@ -7,9 +7,7 @@ CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_CHIP_DIP_SCAN=y
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_DFU_RAM=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/CHIP_pro_defconfig
View File

@ -5,9 +5,7 @@ CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"

2
configs/CSQ_CS908_defconfig
View File

@ -7,8 +7,6 @@ CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SYS_PBSIZE=1024
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y

2
configs/Chuwi_V7_CW0825_defconfig
View File

@ -14,9 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

2
configs/Colombus_defconfig
View File

@ -15,8 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PM1"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SYS_PBSIZE=1024
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

2
configs/Cubieboard2_defconfig
View File

@ -8,9 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/Cubieboard4_defconfig
View File

@ -12,7 +12,5 @@ CONFIG_USB0_ID_DET="PH16"
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
CONFIG_SPL_STACK=0x18000
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y

2
configs/Cubieboard_defconfig
View File

@ -8,9 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

2
configs/Cubietruck_defconfig
View File

@ -13,9 +13,7 @@ CONFIG_SATAPWR="PH12"
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y

2
configs/Cubietruck_plus_defconfig
View File

@ -16,8 +16,6 @@ CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_STACK=0x8000
CONFIG_SYS_PBSIZE=1024
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

2
configs/Empire_electronix_d709_defconfig
View File

@ -16,9 +16,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

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